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Logic Analyzer 的代码
mux4w16.vhd
-- output of CoreGen module generator
-- $Header: mux4VHT.vhd,v 1.2 1998/06/15 17:58:03 tonyw Exp $
-- ************************************************************************
-- Copyright 1996-19
keyncode.vhd
LIBRARY IEEE;----库文件
USE IEEE.STD_LOGIC_1164.ALL;
ENTITY keyncode IS----实体
PORT(
key:IN STD_LOGIC_VECTOR(7 DOWNTO 0);
q: OUT INTEGER RANGE 0 TO 7;
spken: OUT STD_LOGIC);
计数器：generate语句的应用.txt
-- Generated Binary Up Counter
-- The first design entity is a T-type flip-flop.
-- The second is an scalable synchronous binary up counter illustrating the use of the generate statement to produce
mux6_1.vhd
library ieee;
use ieee.std_logic_1164.all;
entity mux6_1 is
port(
sel : in std_logic_vector(2 downto 0);
clk : in std_logic;
datain : in std_logic_vector(9 downto 0);
d
shukongdiv.vhd
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;
ENTITY SHUKONG_DIV IS
PORT(CLK:IN STD_LOGIC;
D:IN STD_LOGIC_VECTOR(7 DOWNTO 0);
FOUT:OUT STD_LOGIC);
END SHUKO
notetabs.vhd
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;
ENTITY NoteTabs IS
PORT ( clk : IN STD_LOGIC;
CounterOUT : OUT STD_LOGIC_VECTOR (7 DOWNTO 0) );
ldpc - behavioral.txt
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
use IEEE.STD_LOGIC_SIGNED.ALL;
entity LDPC is
Port (
clock : in STD_LOGIC;
移位寄存器.txt
--
--
---------------------------------------------------------------------------------------
-- DESCRIPTION : Shift register
-- Type : univ
-- Width : 4
--
shaomiaode.vhd
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;
ENTITY shaomiaode IS
PORT(
CP:IN STD_LOGIC;
SEGOUT :OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
SELOUT :OUT STD_LOGIC_V
zhonghe20.vhd
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;
ENTITY zhonghe20 IS
PORT(
CP,clr,zf,ff :IN STD_LOGIC;
SEGOUT :OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
SELOUT :OUT