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Logic Analyzer 的代码
subc.vhd
-------------------------------------------------------------------------------
-- Title : Parallel-prefix subtractor with carry-in, carry-out
-- Project : VHDL Library of Arithmetic Units
-
subcz.vhd
-------------------------------------------------------------------------------
-- Title : Parallel-prefix subtractor with carry-in, carry-out, zero flag
-- Project : VHDL Library of Arithme
arith_lib.vhd
-------------------------------------------------------------------------------
-- Title : Library component declarations
-- Project : VHDL Library of Arithmetic Units
----------------------
ane.vhd
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
entity ane is
port (cho: in std_logic;
ane: out std_logic);
end entity ane;
architecture one of ane is
signal
system.vhd
-- ------------------------------------------------
-- Model : Top - Level System Component
--
-- Author : Michael Mayer,
-- Department of Electrical Engineering
-- Uni
ramtestbench.th
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
use ieee.std_logic_arith.all;
entity dualram_tb is
end entity;
architecture Behavioral of dualram_tb is
constant
i60bcd.vhd
--The IEEE standard 1164 package, declares std_logic, rising_edge(), etc.
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_arith.all;
use IEEE.std_logic_unsigned.all;
entity i60bcd i
regne.vhd
--regne.vhd n-bit register with enable
library ieee ;
use ieee.std_logic_1164.all ;
entity regne is
generic ( n : integer := 12 ) ;
port (
r : in std_logic_vector(n-1 downto 0) ;--register
negative.vhd
--negative.vhd correct negative number circuit
library ieee ;
use ieee.std_logic_1164.all;
use work.components.all;
entity negative is
port(
a : in std_logic_vector(11 downto 0);--块
bcdadd.vhd
--bcdadd.vhd 1 digit bcd adder
library ieee ;
use ieee.std_logic_1164.all;
use work.components.all;
entity bcdadd is
port(
a : in std_logic_vector(3 downto 0);--砆