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Logic Analyzer 的代码
lut_a_f.vhd
--lut_a_f
library lpm;
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
entity lut_a_f is
port (addr:in std_logic_vector(7 downto 0);
outdata:out std
input_output.vhd
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
-- Uncomment the following lines to use the declarations that are
-- provided for instantia
butterfly1.vhd
library lpm;
use lpm.lpm_components.all;
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
entity butterfly1 is
generic(w2:in
lut_a_f.vhd
--lut_a_f
library lpm;
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
entity lut_a_f is
port (addr:in std_logic_vector(7 downto 0);
outdata:out std
hdpdeps.ref
V1 33
FL G:/vijay_FPGA_LAB/4bit_alu/invtr.vhd 2005/05/25.12:07:16
EN work/INVTR FL G:/vijay_FPGA_LAB/4bit_alu/invtr.vhd \
PB ieee/STD_LOGIC_1164 PB ieee/STD_LOGIC_ARITH PB ieee/STD_
lut_a_f.vhd
--lut_a_f
library lpm;
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
entity lut_a_f is
port (addr:in std_logic_vector(7 downto 0);
outdata:out std
ofdm.vhd
-- ================================================================================
-- File: ofdm.vhd
-- Version: v1.0
-- Author: olivercamel
-- Date: 4.26.2006
-- Description:
-- Top level file
can_registers.vhd
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
use ieee.std_logic_arith.all;
entity can_registers is
port (
clk : in std_logic;
rst : i
ofdm.vhd
-- ================================================================================
-- File: ofdm.vhd
-- Version: v1.0
-- Author: olivercamel
-- Date: 4.26.2006
-- Description:
-- Top level file
keydecoder_deb.vhd
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_ARITH.ALL;
ENTITY keydecoder_deb IS
PORT(
keyin : IN STD_LOGIC_VECTOR(3 DOWNTO 0); --键盘输入
keydrv : IN STD_LOGIC_VECTOR(3 D