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Logic Analyzer 的代码
xspcore.vhd
--------------------------------------------------------------------------------
-- Copyright (c) 2000 by Trenz Electronic.
-- Duenner Kirchweg 77, 32257 Buende, Germany, www.trenz-electronic.de
--
xspuc.vhd
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-- Copyright (c) 2000 by Trenz Electronic.
-- Duenner Kirchweg 77, 32257 Buende, Germany, www.trenz-electronic.de
--
xspusb.vhd
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-- Copyright (c) 2000 by Trenz Electronic.
-- Duenner Kirchweg 77, 32257 Buende, Germany, www.trenz-electronic.de
--
alu.vhd
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
ENTITY alu IS
GENERIC(N: INTEGER := 4);
PORT(A :IN STD_LOGIC_VECTOR(N-1 DOWNTO 0);
B :IN STD_LOGIC_VECTOR(N-1 DOWNTO 0);
Ci :IN
miniuart.vhd
--===========================================================================--
--
-- S Y N T H E Z I A B L E miniUART C O R E
--
-- www.OpenCores.Org - January 2000
-- This core adheres to th
txunit.vhd
--===========================================================================--
--
-- S Y N T H E Z I A B L E miniUART C O R E
--
-- www.OpenCores.Org - January 2000
-- This core adheres to th
txmit_tb.vhd
-- VHDL Test Bench Created from source file txmit.vhd -- 16:58:29 04/12/2000
--
-- Notes:
-- 1) This testbench template has been automatically generated using types
-- std_logic and std_logic_v
command.vhd
--#############################################################################
--
-- LOGIC CORE: Command module
-- MODULE NAME: command()
-- COMPANY: Altera
lcd.vhd
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity lcd is
Port ( clk : in std_logic; --4MHZ FROM D12
Reset
it51_glue.vhd
-------------------------------------------------------------------------------
-- IT51 (Improved-T51) --
--