alu.vhd

实现4位加减乘除的alu

LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
 
ENTITY alu IS
	GENERIC(N:	INTEGER	:=	4);
    PORT(A			:IN		STD_LOGIC_VECTOR(N-1 DOWNTO 0);
		 B			:IN		STD_LOGIC_VECTOR(N-1 DOWNTO 0);
		 Ci			:IN		STD_LOGIC;
         Clk		:IN		STD_LOGIC;
		 load		:IN		STD_LOGIC;
		 optional	:IN		STD_LOGIC_VECTOR(1 DOWNTO 0);
         qout		:OUT	STD_LOGIC_VECTOR(2*N-1 DOWNTO 0);	
		 Co			:OUT	STD_LOGIC;
		 done		:OUT	STD_LOGIC);
END alu;

ARCHITECTURE Behavior OF alu IS
--输出数据
SIGNAL sum		:STD_LOGIC_VECTOR(N-1 DOWNTO 0);
SIGNAL cout		:STD_LOGIC;
SiGNAL diff		:STD_LOGIC_VECTOR(N-1 DOWNTO 0);
SIGNAL bout		:STD_LOGIC;
SIGNAL qout_mul	:STD_LOGIc_VECTOR(2*N-1 DOWNTO 0);
SIGNAL done_mul	:STD_LOGIC;
SIGNAL qout_div	:STD_LOGIC_VECTOR(2*N-1 DOWNTO 0);
SIGNAL done_div	:STD_LOGIC;
--模块引用
COMPONENT fast_add		--加法模块
	GENERIC(N:	INTEGER	:=	4);
    PORT(A		:IN		STD_LOGIC_VECTOR(N-1 DOWNTO 0);
		 B		:IN		STD_LOGIC_VECTOR(N-1 DOWNTO 0);
         Cin	:IN		STD_LOGIC;
         Sum	:OUT	STD_LOGIC_VECTOR(N-1 DOWNTO 0);
         Cout	:OUT	STD_LOGIC);
END COMPONENT;
COMPONENT fast_sub		--减法模块
	GENERIC(N	:INTEGER:= 4);
	PORT( A,B	:IN 	STD_LOGIC_VECTOR(N-1 downto 0);
		  bin	:IN 	STD_LOGIC;
		  Diff	:OUT 	STD_LOGIC_VECTOR(N-1 downto 0);
		  bout	:OUT 	STD_LOGIC);
END COMPONENT;
COMPONENT booth_mul		--乘法模块
	GENERIC(N:	INTEGER	:=	4);
    PORT(A		:IN		STD_LOGIC_VECTOR(N-1 DOWNTO 0);
		 B		:IN		STD_LOGIC_VECTOR(N-1 DOWNTO 0);
         Clk	:IN		STD_LOGIC;
		 load	:IN		STD_LOGIC;
         qout	:OUT	STD_LOGIC_VECTOR(2*N-1 DOWNTO 0);
         done	:OUT	STD_LOGIC);
END COMPONENT;
COMPONENT fast_div		--除法模块
	GENERIC(N:	integer	:=	4);
    PORT(divdend	:IN		STD_LOGIC_VECTOR(N-1 DOWNTO 0);	
		 divisor	:IN		STD_LOGIC_VECTOR(N-1 DOWNTO 0); 
         Clk		:IN		STD_LOGIC;
		 load		:IN		STD_LOGIC;
         qout		:OUT	STD_LOGIC_VECTOR(2*N-1 DOWNTO 0);
         done		:OUT	STD_LOGIC);
END COMPONENT;
BEGIN
	--管脚映射
	add:fast_add GENERIC MAP(N)
	    PORT MAP(A,B,Ci,sum,cout);
	sub:fast_sub GENERIC MAP(N)
		PORT MAP(A,B,Ci,diff,bout);
	mul:booth_mul GENERIC MAP(N)
		PORT MAP(A,B,Clk,load,qout_mul,done_mul);
	div:fast_div GENERIC MAP(N)
		PORT MAP(A,B,Clk,load,qout_div,done_div);
	PROCESS(Clk)
	BEGIN
		IF Clk'EVENT AND Clk = '1' THEN
			CASE optional IS
				WHEN "00" =>	--输出加法结果
					qout(N-1 DOWNTO 0)		<= sum;
					qout(2*N-1 DOWNTO N)	<= (OTHERS => '0');
					co						<= cout;
					done					<= '1';
				WHEN "01" =>	--输出减法结果
					qout(N-1 DOWNTO 0)		<= diff;
					qout(2*N-1 DOWNTO N) 	<= (OTHERS =>'0');
					co						<= bout;
					done					<= '1';
				WHEN "10" =>	--输出乘法结果
					qout					<= qout_mul;
					done					<= done_mul;
				WHEN "11" =>	--输出除法结果
					qout					<= qout_div;
					done					<= done_div;
			END CASE;
		END IF;
	END PROCESS;
END Behavior;