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找到约 10,000 项符合
Logic Analyzer 的代码
txmittest.vhd
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
entity txmittest is
port(
tx:out std_logic;
txclkout:out std_logic;--For test send clok;
data:in std_logic_vecto
xor32.vhd
--xor32
library IEEE;
use IEEE.std_logic_1164.all;
use Ieee.std_logic_unsigned.all;
use Ieee.std_logic_arith.all;
entity xor32 is
port(h1,h2,m1,m2,h3,h4,m3,m4:in std_logic_vector(3 downto 0);
xor32.vhd
--xor32
library IEEE;
use IEEE.std_logic_1164.all;
use Ieee.std_logic_unsigned.all;
use Ieee.std_logic_arith.all;
entity xor32 is
port(h1,h2,m1,m2,h3,h4,m3,m4:in std_logic_vector(3 downto 0);
division10.vhd
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
entity division10 is
port(lin:in std_logic_vector(9 downto 0);
clock:in std_logic;
bsr.vhd
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
entity bsr is
port(din :in std_logic_vector(7 downto 0);
s:in std_logic_vector(2 downto
fen30.vhd
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_ARITH.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;
ENTITY fen30 IS
PORT(
CP : IN STD_LOGIC;
RESET : IN STD_LOGIC;
OV
statmach.vhd
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_ARITH.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;
ENTITY statmach IS
PORT(
CP : IN STD_LOGIC;
RESET : IN STD_LOGIC;
OV
hour1.vhd
Library ieee; --计时模块
Use ieee.std_logic_1164.all;
Use ieee.std_logic_arith.all;
Use ieee.std_logic_unsigned.all;
Entity hour1 is
Port(clkh,set,reset:in std_logic;
h
minute1.vhd
Library ieee; --分钟模块
Use ieee.std_logic_1164.all;
Use ieee.std_logic_arith.all;
Use ieee.std_logic_unsigned.all;
Entity minute1 is
Port(clkm,set,reset:in std_logic;
month1.vhd
Library ieee; --月份模块
Use ieee.std_logic_1164.all;
Use ieee.std_logic_arith.all;
Use ieee.std_logic_unsigned.all;
Entity month1 is
Port(clkd,set,reset:in std_logic;
mo1,mo