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Logic Analyzer 的代码
usbcomm.vhd
library IEEE;
use IEEE.STD_LOGIC_1164.all;
entity USBcomm is
port(
--FPGA信号
A: in STD_LOGIC_VECTOR(15 downto 0); -- 地址总线
DIN: in STD_LOGIC_VECTOR(7 downto 0); -
led.vhd
library IEEE;
use IEEE.STD_LOGIC_1164.all;
entity LED is
port(
A : in STD_LOGIC_VECTOR(15 downto 0); -- 地址总线
WR : in STD_LOGIC; -- 写使能
DWR : in STD_LOGIC_VECTOR(
dct8_slow.txt
-- Top entity is DCT8_slow
-- ENTITY DCT8_slow IS
-- PORT(
-- clk : IN std_logic ;
-- dctselect : IN std_logic ;
-- din : IN std_logic ;
--
b60add2.txt
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
entity b60add2 is
port(clk,clear:in std_logic;
--d:in std_logic_vector(5 downto 0);
co:out std_logic;
q:out
b60add.txt
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
entity b60add is
port(clk,ld,r:in std_logic;
d:in std_logic_vector(5 downto 0);
co:out std_logic;
q:out std_
b60jian2.txt
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
entity b60jian2 is
port(clk,clear:in std_logic;
--d:in std_logic_vector(5 downto 0);
co:out std_logic;
q:out
mc8051_ramx_.vhd
-------------------------------------------------------------------------------
-- --
-- X X XXXXXX XXXXXX
mc8051_rom_.vhd
-------------------------------------------------------------------------------
-- --
-- X X XXXXXX XXXXXX
cpldbus51_tb.vhd
library ieee;
use ieee.STD_LOGIC_UNSIGNED.all;
use ieee.std_logic_1164.all;
entity cpldbus51_tb is
end cpldbus51_tb;
architecture TB_ARCHITECTURE of cpldbus51_tb is
-- Component declaration o
xspcore.vhd
--------------------------------------------------------------------------------
-- Copyright (c) 2000 by Trenz Electronic.
-- Duenner Kirchweg 77, 32257 Buende, Germany, www.trenz-electronic.de
--