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Logic Analyzer 的代码
common.vhd
--------------------------------------------------------------------
-- Company : XESS Corp.
-- Engineer : Dave Vanden Bout
-- Creation Date : 05/17/2005
-- Copyright : 2005, XESS Corp
vga.vhd
--------------------------------------------------------------------
-- Company : XESS Corp.
-- Engineer : Dave Vanden Bout
-- Creation Date : 05/17/2005
-- Copyright : 2005, XESS C
sdramcntl.vhd
library IEEE, UNISIM;
use IEEE.std_logic_1164.all;
package sdram is
-- SDRAM controller
component sdramCntl
generic(
FREQ : natural := 50_000; -- operating
test_vga.vhd
----------------------------------------------------------------------------------
-- This design reads an image from SDRAM and displays it on a VGA monitor
-----------------------------------------
top.vhd
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity top is
Port ( sysclk : in std_logic;
reset1 : in std_logic;
xzq.vhd
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
entity xzq is
port(s1,s2,s3,s4,s5,s6:in std_logic_vector(3 downto 0);
e60,e20,e5:in std_logic;
d1,d0:out std
command.vhd
--
-- LOGIC CORE: Command module
-- MODULE NAME: command()
-- COMPANY: Northwest Logic, Inc.
-- www.nwlogic.com
--
-- REVISION HIST
ddr_command.vhd
--
-- LOGIC CORE: DDR Command module
-- MODULE NAME: ddr_command()
-- COMPANY: Northwest Logic, Inc.
-- www.nwlogic.com
--
-- REVIS
ddr_command.vhd
--
-- LOGIC CORE: DDR Command module
-- MODULE NAME: ddr_command()
-- COMPANY: Northwest Logic, Inc.
-- www.nwlogic.com
--
-- REVIS
xspcore.vhd
--------------------------------------------------------------------------------
-- Copyright (c) 2000 by Trenz Electronic.
-- Duenner Kirchweg 77, 32257 Buende, Germany, www.trenz-electronic.de
--