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Logic Analyzer 的代码
adder.vhd
------------------------------------------------------------------------
-- Single-bit adder
------------------------------------------------------------------------
library IEEE;
use IEEE.std_log
testadder.vhd
entity testbench is
end;
------------------------------------------------------------------------
-- testbench for 8-bit adder
-------------------------------------------------------------------
mc8051_ramx_.vhd
-------------------------------------------------------------------------------
-- --
-- X X XXXXXX XXXXXX
mc8051_rom_.vhd
-------------------------------------------------------------------------------
-- --
-- X X XXXXXX XXXXXX
clock.vhd
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
use ieee.std_logic_arith.all;
entity clock is
port(
s0,s1:in std_logic;
quickclk:in std_logic;
slowclk:in std
xspcore.vhd
--------------------------------------------------------------------------------
-- Copyright (c) 2000 by Trenz Electronic.
-- Duenner Kirchweg 77, 32257 Buende, Germany, www.trenz-electronic.de
--
xspuc.vhd
--------------------------------------------------------------------------------
-- Copyright (c) 2000 by Trenz Electronic.
-- Duenner Kirchweg 77, 32257 Buende, Germany, www.trenz-electronic.de
--
xspusb.vhd
--------------------------------------------------------------------------------
-- Copyright (c) 2000 by Trenz Electronic.
-- Duenner Kirchweg 77, 32257 Buende, Germany, www.trenz-electronic.de
--
bytepermutation.vhd
-------------------------------------------------------------------------------
-- Title : A compact 8bit AES encryption core
-------------------------------------------------------------------
keyexpansion.vhd
-------------------------------------------------------------------------------
-- Title : A compact 8bit AES encryption core
-------------------------------------------------------------------