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找到约 10,000 项符合
Logic Analyzer 的代码
regne.vhd
LIBRARY ieee ;
USE ieee.std_logic_1164.all ;
ENTITY regne IS
GENERIC ( n : INTEGER := 4 ) ;
PORT ( D : IN STD_LOGIC_VECTOR(n-1 DOWNTO 0) ;
Resetn : IN STD_LOGIC ;
E, Clock : IN
latch.vhd
LIBRARY ieee ;
USE ieee.std_logic_1164.all ;
ENTITY latch IS
PORT ( D, clk : IN STD_LOGIC ;
Q : OUT STD_LOGIC ) ;
END latch ;
ARCHITECTURE Behavior OF latch IS
BEGIN
PR
regne.vhd
LIBRARY ieee ;
USE ieee.std_logic_1164.all ;
ENTITY regne IS
GENERIC ( n : INTEGER := 4 ) ;
PORT ( D : IN STD_LOGIC_VECTOR(n-1 DOWNTO 0) ;
Resetn : IN STD_LOGIC ;
E, Clock : IN
components.vhd
LIBRARY ieee ;
USE ieee.std_logic_1164.all ;
PACKAGE components IS
COMPONENT addern -- n-bit adder
GENERIC ( n : INTEGER := 4 ) ;
PORT ( Cin : IN STD_LOGIC ;
X, Y : IN STD_LO
components.vhd
LIBRARY ieee ;
USE ieee.std_logic_1164.all ;
PACKAGE components IS
COMPONENT addern -- n-bit adder
GENERIC ( n : INTEGER := 4 ) ;
PORT ( Cin : IN STD_LOGIC ;
X, Y : IN STD_LO
serial.vhd
LIBRARY ieee ;
USE ieee.std_logic_1164.all ;
ENTITY serial IS
GENERIC ( length : INTEGER := 8 ) ;
PORT ( Clock : IN STD_LOGIC ;
Reset : IN STD_LOGIC ;
A, B : IN STD_LOGIC_VECT
shiftrne.vhd
LIBRARY ieee ;
USE ieee.std_logic_1164.all ;
-- left-to-right shift register with parallel load and enable
ENTITY shiftrne IS
GENERIC ( N : INTEGER := 4 ) ;
PORT ( R : IN STD_LOGIC_VECTO
shiftrne.vhd
LIBRARY ieee ;
USE ieee.std_logic_1164.all ;
-- left-to-right shift register with parallel load and enable
ENTITY shiftrne IS
GENERIC ( N : INTEGER := 4 ) ;
PORT ( R : IN STD_LOGIC_VECTO
regne.vhd
LIBRARY ieee ;
USE ieee.std_logic_1164.all ;
ENTITY regne IS
GENERIC ( N : INTEGER := 4 ) ;
PORT ( R : IN STD_LOGIC_VECTOR(N-1 DOWNTO 0) ;
Resetn : IN STD_LOGIC ;
E, Clock : IN
components.vhd
LIBRARY ieee;
USE ieee.std_logic_1164.all;
PACKAGE components IS
COMPONENT mux2to1 -- 2-to-1 multiplexer
PORT ( w0, w1 : IN STD_LOGIC ;
s : IN STD_LOGIC ;
f : OUT STD_LOGIC );