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Logic Analyzer 的代码
command.vhd
--#############################################################################
--
-- LOGIC CORE: Command module
-- MODULE NAME: command()
-- COMPANY: Altera
latch.vhd
LIBRARY ieee ;
USE ieee.std_logic_1164.all ;
ENTITY latch IS
PORT ( D, Clk : IN STD_LOGIC ;
Q : OUT STD_LOGIC) ;
END latch ;
ARCHITECTURE Behavior OF latch IS
BEGIN
PRO
shift.vhd
LIBRARY ieee ;
USE ieee.std_logic_1164.all ;
LIBRARY lpm ;
USE lpm.lpm_components.all ;
ENTITY shift IS
PORT ( Clock : IN STD_LOGIC ;
Reset : IN STD_LOGIC ;
Shiftin, Load :
subccts.vhd
LIBRARY ieee ;
USE ieee.std_logic_1164.all ;
PACKAGE subccts IS
COMPONENT regn
GENERIC ( N : INTEGER := 8 ) ;
PORT ( R : IN STD_LOGIC_VECTOR(N-1 DOWNTO 0) ;
Rin, Clock : IN STD_L
proc.vhd
LIBRARY ieee ;
USE ieee.std_logic_1164.all ;
USE ieee.std_logic_signed.all ;
USE work.subccts.all ;
ENTITY proc IS
PORT ( Data : IN STD_LOGIC_VECTOR(7 DOWNTO 0) ;
Reset, w : IN STD_
subccts.vhd
LIBRARY ieee ;
USE ieee.std_logic_1164.all ;
PACKAGE subccts IS
COMPONENT regn
GENERIC ( N : INTEGER := 8 ) ;
PORT ( R : IN STD_LOGIC_VECTOR(N-1 DOWNTO 0) ;
Rin, Clock : IN STD_L
shiftn.vhd
LIBRARY ieee ;
USE ieee.std_logic_1164.all ;
ENTITY shiftn IS
GENERIC ( N : INTEGER := 8 ) ;
PORT ( R : IN STD_LOGIC_VECTOR(N-1 DOWNTO 0) ;
Clock : IN STD_LOGIC ;
L, w : IN S
implied.vhd
LIBRARY ieee ;
USE ieee.std_logic_1164.all ;
ENTITY implied IS
PORT ( A, B : IN STD_LOGIC ;
AeqB : OUT STD_LOGIC ) ;
END implied ;
ARCHITECTURE Behavior OF implied IS
BEGIN
PROCE
implied.vhd
LIBRARY ieee ;
USE ieee.std_logic_1164.all ;
ENTITY implied IS
PORT ( A, B : IN STD_LOGIC ;
AeqB : OUT STD_LOGIC ) ;
END implied ;
ARCHITECTURE Behavior OF implied IS
BEGIN
PROCE
flipflop.vhd
LIBRARY ieee ;
USE ieee.std_logic_1164.all ;
ENTITY flipflop IS
PORT ( D, Clock : IN STD_LOGIC ;
Q : OUT STD_LOGIC ) ;
END flipflop ;
ARCHITECTURE Behavior OF flipflop IS