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Logic Analyzer 的代码
msscomppackage.vhd
-- *****************************************************************************************
-- Components for ARM memory subsystem (simulation)
-- Designed by Ruslan Lepetenok
-- Modified 02.02.20
mulctrlandregs.vhd
--****************************************************************************************************
-- Multiplier control and Partial Sum/Carry registers for ARM core
-- Designed by Ruslan Lepete
multipliertestadder.vhd
--****************************************************************************************************
-- Adder for multiplier tester for ARM core
-- Designed by Ruslan Lepetenok
-- Modified 27.01.
arm7tdmis_top.vhd
--****************************************************************************************************
-- Top entity for ARM7TDMI-S processor
-- Designed by Ruslan Lepetenok
-- Modified 05.02.2003
multiplier.vhd
--****************************************************************************************************
-- Multiplier for ARM core
-- Designed by Ruslan Lepetenok
-- Modified 07.12.2002
--*********
regs_pkg.vhd
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
package regs_pkg is
component rdff1 port(
clk,reset:in std_logic;
d: in std_logic;
reg.vhd
-- Register set
-- size:(size) a generic
--
-- clk--posedge clock input
-- rst--asynchronous reset
-- pst--asynchronous preset
-- load--active high input loads register
-- d--register input
--
topcon.vhd
--###############################################################################
--
-- LOGIC CORE: SDR SDRAM Controller
-- MODULE NAME: Controller()
-- da
controller.vhd
--###############################################################################
--
-- LOGIC CORE: SDR SDRAM Controller
-- MODULE NAME: Controller()
-
command.vhd
--#############################################################################
--
-- LOGIC CORE: Command module
-- MODULE NAME: command()
-- COMPANY: Altera Cor