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Logic Analyzer 的代码
counter24.vhd
--******************************************************
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_ARITH.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;
--****************************
rom16_8.vhd
-- ********************************************
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_ARITH.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;
--*************************************
txmittest.vhd
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
entity txmittest is
port(
tx:out std_logic;
txclkout:out std_logic;--For test send clok;
data:in std_logic_vecto
xor32.vhd
--xor32
library IEEE;
use IEEE.std_logic_1164.all;
use Ieee.std_logic_unsigned.all;
use Ieee.std_logic_arith.all;
entity xor32 is
port(h1,h2,m1,m2,h3,h4,m3,m4:in std_logic_vector(3 downto 0);
xor32.vhd
--xor32
library IEEE;
use IEEE.std_logic_1164.all;
use Ieee.std_logic_unsigned.all;
use Ieee.std_logic_arith.all;
entity xor32 is
port(h1,h2,m1,m2,h3,h4,m3,m4:in std_logic_vector(3 downto 0);
division10.vhd
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
entity division10 is
port(lin:in std_logic_vector(9 downto 0);
clock:in std_logic;
bsr.vhd
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
entity bsr is
port(din :in std_logic_vector(7 downto 0);
s:in std_logic_vector(2 downto
bl.vhd
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_arith.all;
use IEEE.std_logic_unsigned.all;
entity bl is
port (
BLCLK: in STD_LOGIC;
reset :in std_logic;
changgel11.tdf
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_arith.all;
use IEEE.std_logic_unsigned.all;
entity changedl is
port (
ADDR: in STD_LOGIC_VECTOR (5 downto 0);
filter_liqiong.vhd
library IEEE;
use IEEE.std_logic_1164.all;
library xp2;
use xp2.components.all;
entity FILTER is
Port ( rst : In std_logic;
sdi : In std_logic;