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-- A Variety of Adder Styles -- download from: www.fpga.com.cn & www.pld.com.cn ------------------------------------------------------------------------ -- Single-bit adder -----------------------

LIBRARY IEEE; USE IEEE.STD_LOGIC_1164.ALL; USE IEEE.STD_LOGIC_UNSIGNED.ALL; ENTITY clock IS PORT (set,date,clo,clk,rst : IN STD_LOGIC; co1,co2,co3,co4,co5,co6 : OUT STD_LOGIC_VECTO

-- testbench for VHDL library IEEE; library work; use IEEE.std_logic_1164.all; use IEEE.STD_LOGIC_ARITH.ALL; use IEEE.STD_LOGIC_UNSIGNED.ALL; entity testbench is -- port (data : inout std_logic_vecto

library IEEE; use IEEE.std_logic_1164.all; entity shifter is port ( clk, rst: in std_logic; shiftEn,shiftIn: std_logic; q: out std_logic_vector (15 downto 0) ); end shifter; arch

library IEEE; use IEEE.std_logic_1164.all; use IEEE.std_logic_unsigned.all; entity BidirCnt is port ( OE: in std_logic; CntEnable: in std_logic; LdCnt: in std_logic; Clk: in std_logic

-- Incorporates Errata 5.4 library ieee; use ieee.std_logic_1164.all; use ieee.numeric_std.all; entity counter is port ( clk: in std_logic; reset: in std_logic; load: in std_logic;

-- Incorporates Errata 5.4 library ieee; use ieee.std_logic_1164.all; use ieee.numeric_std.all; entity counter is port ( clk: in std_logic; reset: in std_logic; load: in std_logic;

library IEEE; use IEEE.std_logic_1164.all; entity DFF is port ( d: in std_logic; clk: in std_logic; envector: in std_logic_vector(7 downto 0); q: out std_logic ); end DFF

library IEEE; use IEEE.std_logic_1164.all; package primitive is component DFFE port ( d: in std_logic; q: out std_logic; en: in std_logic; clk: in std_logic ); end c

---------------------------------------------------------------------------- -- This file is a part of the LEON VHDL model -- Copyright (C) 1999 European Space Agency (ESA) -- -- This library is