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Logic Analyzer 的代码
ex_3_8_overload.vhd
entity overload is end overload;
architecture beh of overload is
Type LOGIC4 is ('0','1','Z','X');
Type L4_TWO_DIM_ARR is
array(LOGIC4,LOGIC4) of LOGIC4;
Type L4_ONE_DIM_ARR is
division10.vhd
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
entity division10 is
port(lin:in std_logic_vector(9 downto 0);
clock:in std_logic;
usbcomm.vhd
library IEEE;
use IEEE.STD_LOGIC_1164.all;
entity USBcomm is
port(
--FPGA信号
A: in STD_LOGIC_VECTOR(15 downto 0); -- 地址总线
DIN: in STD_LOGIC_VECTOR(7 downto 0); -
led.vhd
library IEEE;
use IEEE.STD_LOGIC_1164.all;
entity LED is
port(
A : in STD_LOGIC_VECTOR(15 downto 0); -- 地址总线
WR : in STD_LOGIC; -- 写使能
DWR : in STD_LOGIC_VECTOR(
txmittest.vhd
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
entity txmittest is
port(
tx:out std_logic;
txclkout:out std_logic;--For test send clok;
data:in std_logic_vecto
bsr.vhd
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
entity bsr is
port(din :in std_logic_vector(7 downto 0);
s:in std_logic_vector(2 downto
dds.txt
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_arith.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;
ENTITY DDS IS
PORT (clk :IN STD_LOGIC;
K:IN STD_LOGIC_VECTOR(9 DOWNTO 0);
RESET:IN S
dds.txt
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_arith.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;
ENTITY DDS IS
PORT (clk :IN STD_LOGIC;
K:IN STD_LOGIC_VECTOR(9 DOWNTO 0);
RESET:IN S
lcd.vhd
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity lcd is
Port ( clk : in std_logic; --3.125MHZ FROM div16 Module
blowfishsbox.vhdl
-- Copyright © 2007 Wesley J. Landaker
--
-- This program is free software: you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as publis