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找到约 10,000 项符合 Logic Analyzer 的代码

multipliertestadder.vhd

--**************************************************************************************************** -- Adder for multiplier tester for ARM core -- Designed by Ruslan Lepetenok -- Modified 27.01.

arm7tdmis_top.vhd

--**************************************************************************************************** -- Top entity for ARM7TDMI-S processor -- Designed by Ruslan Lepetenok -- Modified 12.02.2003

multiplier.vhd

--**************************************************************************************************** -- Multiplier for ARM core -- Designed by Ruslan Lepetenok -- Modified 12.02.2003 --*********

加法器源程序.vhd

------------------------------------------------------------------------ -- Single-bit adder ------------------------------------------------------------------------ library IEEE; use IEEE.std_log

加法器描述.txt

-- A Variety of Adder Styles -- download from: www.fpga.com.cn & www.pld.com.cn ------------------------------------------------------------------------ -- Single-bit adder -----------------------

相应加法器的测试向量（test bench).vhd

-- download from: www.pld.com.cn & www.fpga.com.cn entity testbench is end; ------------------------------------------------------------------------ -- testbench for 8-bit adder ------------

stopwatch.vhd

library ieee; use ieee.std_logic_1164.all; use ieee.std_logic_arith.all; use ieee.std_logic_unsigned.all; entity stopwatch is port(reset :in std_logic; on_off :in std_logic; sysreset:in

serial_generatedinstance.vhd

-------------------------------------------------- -- Model : 8051 Behavioral Model, -- VHDL Entity mc8051.serial.generatedInstance -- -- Author : Michael Mayer (mrma

butterfly0_entity3.vhd

-- ------------------------------------------------------------- -- -- Module: Butterfly0_entity3 -- Simulink Path: hdlcoderviterbi/viterbi_block/ACS Unit/ACS/Subsystem11/Butterfly0 -- Created: 2009-0

subsystem12.vhd

-- ------------------------------------------------------------- -- -- Module: Subsystem12 -- Simulink Path: hdlcoderviterbi/viterbi_block/ACS Unit/ACS/Subsystem12 -- Created: 2009-03-24 16:23:27 -- H