stopwatch.vhd

一个用VHDL编写的秒表程序

library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;

entity stopwatch is
	port(reset	:in std_logic;
		on_off	:in std_logic;
		sysreset:in std_logic;
		clk		:in std_logic;
		choose	:out std_logic_vector(7 downto 0);
		segment	:out std_logic_vector(6 downto 0)
		);
end stopwatch;

architecture structure of stopwatch is
	component keyin
		port(reset	:in std_logic;
			on_off	:in std_logic;
			clk		:in std_logic;
			clk1	:in std_logic;
			reset0	:out std_logic;
			on_off0	:out std_logic
			);
	end	component;
	
	component clk_div
		port(sysreset	:in std_logic;
			clk			:in std_logic;
			clk0		:out std_logic;
			clk1		:out std_logic
			);
	end component;
	
	component control1
		port(sysreset:in std_logic;
			reset0	:in std_logic;
			on_off0	:in std_logic;
			clk0	:in std_logic;
			enable	:out std_logic
			);
	end component;
	
	component time_counter
		port(sysreset	:in std_logic;
			reset0	:in std_logic;
			clk0	:in std_logic;
			enable	:in std_logic;
			hr10	:out std_logic_vector(3 downto 0);
			hr		:out std_logic_vector(3 downto 0);
			min10	:out std_logic_vector(2 downto 0);
			min 	:out std_logic_vector(3 downto 0);
            sec10	:out std_logic_vector(2 downto 0);
            sec 	:out std_logic_vector(3 downto 0);
            sec01	:out std_logic_vector(3 downto 0);
            sec001	:out std_logic_vector(3 downto 0)       
			);
	end component;
	
	component display
		port(sysreset	:in std_logic;
			clk		:in std_logic;
			hr10	:in std_logic_vector(3 downto 0);
			hr		:in std_logic_vector(3 downto 0);
			min10	:in std_logic_vector(2 downto 0);
			min 	:in std_logic_vector(3 downto 0);
            sec10	:in std_logic_vector(2 downto 0);
            sec 	:in std_logic_vector(3 downto 0);
            sec01	:in std_logic_vector(3 downto 0);
            sec001	:in std_logic_vector(3 downto 0);
			choose	:out std_logic_vector(7 downto 0);
			segment	:out std_logic_vector(6 downto 0)      
			);
	end component;
	
	signal reset0	:std_logic;
	signal on_off0	:std_logic;
	signal clk0		:std_logic;	
	signal clk1		:std_logic;	
	signal enable	:std_logic;
	signal hr10		:std_logic_vector(3 downto 0);
	signal hr		:std_logic_vector(3 downto 0);
	signal min10	:std_logic_vector(2 downto 0);
	signal min 		:std_logic_vector(3 downto 0);
    signal sec10	:std_logic_vector(2 downto 0);
    signal sec 		:std_logic_vector(3 downto 0);
    signal sec01	:std_logic_vector(3 downto 0);
    signal sec001	:std_logic_vector(3 downto 0);
 begin
	u0:keyin
		port map(reset,on_off,clk,clk1,reset0,on_off0);
	u1:clk_div
		port map(sysreset,clk,clk0,clk1);
	u2:control1
		port map(sysreset,reset0,on_off0,clk0,enable);
	u3:time_counter
		port map(sysreset,reset0,enable,clk0,hr10,hr,min10,min,sec10,sec,sec01,sec001);
	u4:display
		port map(sysreset,clk,hr10,hr,min10,min,sec10,sec,sec01,sec001,choose,segment);
end structure;