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Logic Analyzer 的代码
sck_logic.vhd
-- File: sck_logic.vhd
--
-- Created: 8-23-00 ALS
-- This file generates an internal SCK by dividing the system clock as determined by CLKDIV.
-- This internal SCK has a CPHA=1 relationshi
struts-logic.html
The Struts Fram
dev_logic.html
The Struts User
logic_legxbr.htm
I/O Style - OD - OpenDrain
- PU - Pullup
- KPR - Keeper
- S - SchmittTrigger
- DG - DataGate
Reg Use - LATCH - Transparent la
logic_control.vhd
Library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
use ieee.std_logic_arith.all;
entity logic_control is
port(
clk,start: in std_logic;
clr,addclk,OE: o
logic_control.bsf
/*
WARNING: Do NOT edit the input and output ports in this file in a text
editor if you plan to continue editing the block that represents it in
the Block Editor! File corruption is VERY likely to