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Logic Analyzer 的代码
sram16.vhd
-----------------------------------------------------------------------------
-- This file is a part of the GRLIB VHDL IP LIBRARY
-- Copyright (C) 2004 GAISLER RESEARCH
--
-- This program is free s
ioport.vhd
----------------------------------------------------------------------------
-- This file is a part of the LEON VHDL model
-- Copyright (C) 1999 European Space Agency (ESA)
--
-- This library
cache_comp.vhd
-- $(lic)
-- $(help_generic)
-- $(help_local)
library IEEE;
use IEEE.std_logic_1164.all;
use work.amba.all;
use work.config.all;
use work.cache_config.all;
use work.corelib.all;
use work.ge
uart_5kvg_top.vhd
-- --------------------------------------------------------------------
-- >>>>>>>>>>>>>>>>>>>>>>>>> COPYRIGHT NOTICE
uart_top.vhd
-- --------------------------------------------------------------------
-- >>>>>>>>>>>>>>>>>>>>>>>>> COPYRIGHT NOTICE
加法器源程序.vhd
------------------------------------------------------------------------
-- Single-bit adder
------------------------------------------------------------------------
library IEEE;
use IEEE.std_log
加法器描述.txt
-- A Variety of Adder Styles
-- download from: www.fpga.com.cn & www.pld.com.cn
------------------------------------------------------------------------
-- Single-bit adder
-----------------------
相应加法器的测试向量（test bench).vhd
-- download from: www.pld.com.cn & www.fpga.com.cn
entity testbench is
end;
------------------------------------------------------------------------
-- testbench for 8-bit adder
------------
sdram_ctrl1.vhd
------------------------------------------------------------------
--
-- sdram_ctrl.vhd
--
components.vhd
-- PACKAGE :COMPONENTS:
library ieee;
use ieee.std_logic_1164.all;
package components is
component data_bus_buffer
port(dmp : inout std_logic_vector(7 downto 0);
drd : ou