components.vhd

USART coded in VHDL. It is writted in 5 files. I am uploading the files in order.

			--		PACKAGE :COMPONENTS:

library ieee;
use ieee.std_logic_1164.all;

package components is
	
component data_bus_buffer
port(dmp					: inout	std_logic_vector(7 downto 0);
		drd						: out		std_logic_vector(7 downto 0);
		dwr						: in		std_logic_vector(7 downto 0);
		en						: in		std_logic );
end component;				

component rd_wr_control
port(reset				: in		std_logic;
		clk						: in		std_logic;
		cd						: in		std_logic;
		rd						: in		std_logic;	
		wr						: in		std_logic;
		cs						: in		std_logic;
		drd						: in		std_logic_vector(7 downto 0);
		dwr						: out		std_logic_vector(7 downto 0);
		ciport				: out		std_logic_vector(7 downto 0);
		miport				: out		std_logic_vector(7 downto 0);
		syn1port			: out		std_logic_vector(7 downto 0);
		syn2port			: out		std_logic_vector(7 downto 0);
		holdport			: out		std_logic_vector(7 downto 0);
		writeport 		: in		std_logic_vector(7 downto 0);
		statusport		: out		std_logic_vector(7 downto 0);
		en						: out		std_logic;
		holdreg_emp		: in		std_logic;
		cts						: in		std_logic;
		dsr						: in 	  std_logic;
		hold_cts			: out		std_logic;
		txe_status		: in		std_logic;
		syndet_status	: in		std_logic;
		rxrdy_status	: in	 	std_logic;
		parity_error	: in	 	std_logic;
		framing_error	: in		std_logic;
		overrun_error	: in		std_logic;
		status_read		: out		std_logic;
		data_read			: out		std_logic );
end component;
									   
component modem_control
port(dsr					: in		std_logic;
		dtr						: out		std_logic;
		cts						: in 		std_logic;
		rts						: out		std_logic;
		modemclear		: out		std_logic;
		ciport				: in		std_logic_vector(7 downto 0));
end component;
					
component tx_buff
port(ciport				: in		std_logic_vector(7 downto 0);
		miport				: in		std_logic_vector(7 downto 0);
		syn1port			: in		std_logic_vector(7 downto 0);
		syn2port			: in		std_logic_vector(7 downto 0);
		holdport			: in		std_logic_vector(7 downto 0);
		statusport		: in		std_logic_vector(7 downto 0);
		holdreg_emp		: out		std_logic;
		txclk					: in		std_logic;
		txrdy					: out		std_logic;
		txe						: out		std_logic;
		txd						: out		std_logic; 
		modemclear		: in		std_logic;
		clk						: in		std_logic;
		hold_cts			: in		std_logic;
		txe_status		: out		std_logic );
end component;	 
						

component rec_buf 
port(ciport				: in		std_logic_vector(7 downto 0);
		miport				: in		std_logic_vector(7 downto 0);
		syn1port			: in		std_logic_vector(7 downto 0);
		syn2port			: in		std_logic_vector(7 downto 0);
		statusport		: in		std_logic_vector(7 downto 0);
		writeport			: out		std_logic_vector(7 downto 0);
		rxclk					: in		std_logic;
		rxrdy					: out		std_logic;
		rxd						: in		std_logic; 
		syndet 				: inout	std_logic;
		parity_error	: out		std_logic;
		framing_error	: out		std_logic;
		overrun_error	: out		std_logic;
		syndet_status	: out		std_logic; 
		status_read		: in		std_logic;
		data_read			: in		std_logic;	
		rxrdy_status	: out		std_logic );
end component;	

end components;