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Logic Analyzer 的代码
61_logic.vhd
library IEEE;
use IEEE.std_logic_1164.all;
package logic_pack is
function resolve(s : std_ulogic_vector) return std_ulogic;
SUBTYPE logic is resolve std_ulogic;
TYPE logic_vector IS ARRAY
vga_logic.vqm
// Copyright (C) 1991-2005 Altera Corporation
// Your use of Altera Corporation's design tools, logic functions
// and other software and tools, and its AMPP partner logic
// functions, and
frm_logic.frm
VERSION 5.00
Object = "{831FDD16-0C5C-11D2-A9FC-0000F8754DA1}#2.0#0"; "MSCOMCTL.OCX"
Object = "{67397AA1-7FB1-11D0-B148-00A0C922E820}#6.0#0"; "MSADODC.OCX"
Begin VB.Form frm_load
BorderStyle
jtag_logic.vhd
-------------------------------------------------------------------------------
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_unsigned.all;
----------------------------------------
logic_legxbr.htm
I/O Style - OD - OpenDrain
- PU - Pullup
- KPR - Keeper
- S - SchmittTrigger
- DG - DataGate
Reg Use - LATCH - Transparent la