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Logic Analyzer 的代码
clock.vhd
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
entity clock is
port (clk:in std_logic;
en,rst:in std_logic;
th_set:in std_logic;
h_set:in std_l
sin.vhd
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_unsigned.all;
entity sin is
port(
clk : in std_logic;
fword : in std_logic_vector(7 downto 0);
dout : out std_logic_vector(7 d
division.vhd
library IEEE;
use IEEE.STD_LOGIC_1164.all;
use IEEE.STD_LOGIC_UNSIGNED.all;
use IEEE.STD_LOGIC_ARITH.all;
entity division is
generic(SIZE: INTEGER := 8);
port(reset: in STD_LOGI
top_struct.vhd
-------------------------------------------------------------------------------
-- --
-- 8086VGA - VHDL 8086/8088 VGA IP co
pio_rtl.vhd
-------------------------------------------------------------------------------
-- --
-- CPU86 - VHDL CPU8088 IP core
dac2adc.vhd
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;
ENTITY DAC2ADC IS
PORT ( CLK : IN STD_LOGIC; --计数器时钟
LM311 : IN STD_LOGIC; --LM311输出，由PIO37口进入FPG
ball.vhd
--乒乓球灯模块
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
entity ball is
port(clk:in std_logic;--乒乓球灯前进时钟
clr:in std_logic;--乒乓球灯清零
way:in std_logic;--乒乓球灯前进方向
en
加法器源程序 (2).txt
------------------------------------------------------------------------
-- Single-bit adder
------------------------------------------------------------------------
library IEEE;
use IEEE.std_log
加法器描述.txt
-- A Variety of Adder Styles
-- download from: www.fpga.com.cn & www.pld.com.cn
------------------------------------------------------------------------
-- Single-bit adder
-----------------------
相应加法器的测试向量（test bench).txt
-- download from: www.pld.com.cn & www.fpga.com.cn
entity testbench is
end;
------------------------------------------------------------------------
-- testbench for 8-bit adder
------------