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Logic Analyzer 的代码
pci.cmp
-- Generated by PCI Compiler 4.1.1 [Altera, IP Toolbench v1.2.11 build48]
-- ************************************************************
-- THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
ihdlutil.vhd
--
-- interHDL proprietary information
-- Copyright (C) 1990-1998 interHDL inc.
-- All rights reserved.
--
-- ihdlutil package. produced by interVHDL (R)
-- ihdlutil package. Implements utility functi
newclock.txt
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
entity newclock is
port(clk :in std_logic;
segout :out std_logic_vector(7 downt
newclock.vhd.txt
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
entity newclock is
port(clk :in std_logic;
segout :out std_logic_vector(7 downt
interfazv1.vhd
library IEEE;
use IEEE.std_logic_1164.all;
entity interfaz is
port (
clk: in STD_LOGIC;
resetz: in STD_LOGIC;
data: in STD_LOGIC_VECTOR(5 downto 0);
habili
a8255.vhd
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
ENTITY a8255 IS
PORT(
RESET : IN std_logic;
CLK : IN std_logic;
nCS : IN std_logic;
nRD : IN std_logic;
nWR
dff89.vhd
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
ENTITY dff89 IS
PORT( clk : IN STD_LOGIC;
clear : IN STD_LOGIC;
Din : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
Dout : OUT STD_LOGIC_VECTO
dff15.vhd
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
ENTITY dff15 IS
PORT( clk : IN STD_LOGIC;
clear : IN STD_LOGIC;
Din : IN STD_LOGIC_VECTOR(15 DOWNTO 0);
Dout : OUT STD_LOGIC_VECT
dff8.vhd
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
ENTITY dff8 IS
PORT( clk : IN STD_LOGIC;
clear : IN STD_LOGIC;
Din : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
Dout : OUT STD_LOGIC_V
dac2adc.vhd
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;
ENTITY DAC2ADC IS
PORT ( CLK : IN STD_LOGIC; --计数器时钟
LM311 : IN STD_LOGIC; --LM311输出，由PIO37口进入FPG