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Logic Analyzer 的代码
cnt25.vhd
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;
ENTITY CNT25 IS
PORT( CLK:IN STD_LOGIC;
EN:IN STD_LOGIC;
S2:OUT STD_LOGIC;
LOAD:IN BIT;
Q2
cnt5.vhd
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;
ENTITY CNT5 IS
PORT( CLK:IN STD_LOGIC;
EN:IN STD_LOGIC;
S1:OUT STD_LOGIC;
LOAD:IN BIT;
Q1:
cnt50.vhd
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;
ENTITY CNT50 IS
PORT( CLK:IN STD_LOGIC;
EN:IN STD_LOGIC;
S5:OUT STD_LOGIC;
LOAD:IN BIT;
Q5
cnt45.vhd
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;
ENTITY CNT45 IS
PORT( CLK:IN STD_LOGIC;
EN:IN STD_LOGIC;
S4:OUT STD_LOGIC;
LOAD:IN BIT;
Q4
bl.vhd
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
entity bl is
PORT(
C:in std_logic_vector(2 downto 0);
opcode:in std_logic_vector(7 downto 0);
downto0: in
car.vhd
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
entity car is
port(
cin: in std_logic_vector(7 downto 0);
add1,load,reset,clk: in std_logic;
加法器源程序.vhd
------------------------------------------------------------------------
-- Single-bit adder
------------------------------------------------------------------------
library IEEE;
use IEEE.std_log
加法器描述.txt
-- A Variety of Adder Styles
-- download from: www.fpga.com.cn & www.pld.com.cn
------------------------------------------------------------------------
-- Single-bit adder
-----------------------
相应加法器的测试向量（test bench).vhd
-- download from: www.pld.com.cn & www.fpga.com.cn
entity testbench is
end;
------------------------------------------------------------------------
-- testbench for 8-bit adder
------------
select_32.vhd
library ieee;
use ieee.std_logic_1164.all;
entity select_32 is
port( A:in std_logic_vector(15 downto 0);
B:in std_logic_vector(15 downto 0);
S:in std_logic;
Y:out std_logic_vector(15