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Logic Analyzer 的代码
rgec5_2.vhd
--------------------------------------------------------------------------------
--
-- File : rgec5_2.vhd
-- Last Modification: 06/26/2001
--
-- Created In SpDE Version: SpDE 8.22
-- Author : Ri
gcnte5_0.vhd
--------------------------------------------------------------------------------
--
-- File : gcnte5_0.vhd
-- Last Modification: 06/26/2001
--
-- Created In SpDE Version: SpDE 8.22
-- Author : R
gcnte5_2.vhd
--------------------------------------------------------------------------------
--
-- File : gcnte5_2.vhd
-- Last Modification: 06/26/2001
--
-- Created In SpDE Version: SpDE 8.22
-- Author : R
iface.vhd
----------------------------------------------------------------------------
-- This file is a part of the LEON VHDL model
-- Copyright (C) 1999 European Space Agency (ESA)
--
-- This library
leon_eth.vhd
----------------------------------------------------------------------------
-- This file is a part of the LEON VHDL model
-- Copyright (C) 1999 European Space Agency (ESA)
--
-- This library
ahbstat.vhd
----------------------------------------------------------------------------
-- This file is a part of the LEON VHDL model
-- Copyright (C) 1999 European Space Agency (ESA)
--
-- This library
usb_new_usbvpb_top_str.vhdl
--------------------------------------------------------------------------------
--
-- P H I L I P S C O M P A N Y R E S T R I C T E D
--
-- Copyright
usb_new_usbpvci_ent.vhdl
--------------------------------------------------------------------------------
--
-- P H I L I P S C O M P A N Y R E S T R I C T E D
--
-- Copyright
rom.vhd
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_ARITH.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;
ENTITY rom IS
PORT(
dataout:OUT STD_LOGIC_VECTOR(7 DOWNTO 0);--数据输出
addr:IN S
mx_7821.vhd.bak
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
entity mx_7821 is
port (clk: in std_logic;
din: in std_logic_vector (7 downto