📄 rom.vhd
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LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_ARITH.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;
ENTITY rom IS
PORT(
dataout:OUT STD_LOGIC_VECTOR(7 DOWNTO 0);--数据输出
addr:IN STD_LOGIC_VECTOR(3 DOWNTO 0);--地址
ce:IN STD_LOGIC);--使能
END rom;
ARCHITECTURE rt1 OF rom IS
BEGIN
dataout<="00001001" WHEN addr="0000" AND ce='0' ELSE
"00011010" WHEN addr="0001" AND ce='0' ELSE
"00011011" WHEN addr="0010" AND ce='0' ELSE
"00101100" WHEN addr="0011" AND ce='0' ELSE
"11100000" WHEN addr="0100" AND ce='0' ELSE
"11110000" WHEN addr="0101" AND ce='0' ELSE
"00010000" WHEN addr="1001" AND ce='0' ELSE
"00010100" WHEN addr="1010" AND ce='0' ELSE
"00011000" WHEN addr="1011" AND ce='0' ELSE
"00100000" WHEN addr="1100" AND ce='0' ELSE
"00000000";
END rt1;
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