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Logic Analyzer 的代码
counter16.vhd
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
entity counter16 is
port(
clr: in std_logic;
fin: IN std_logic;
start: in std_logic;
Q
counter16.vhd.bak
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
entity counter16 is
port(
clr: in std_logic;
fin: IN std_logic;
start: in std_logic;
Q
pci_core.cmp
-- Generated by PCI Compiler 4.0.0 [Altera, IP Toolbench v1.2.9 build44]
-- ************************************************************
-- THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
-
pci_top.cmp
-- Generated by PCI Compiler 4.0.0 [Altera, IP Toolbench v1.2.9 build44]
-- ************************************************************
-- THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
-
tb.vhd
--*******************************************************************--
-- Copyright (c) 1999-2001 Evatronix SA --
--****************************************************
c8051.vhd
--*******************************************************************--
-- Copyright (c) 1999-2001 Evatronix SA --
--****************************************************
avr_core.vhd
--************************************************************************************************
-- Top entity for AVR core
-- Version 1.11
-- Designed by Ruslan Lepetenok
-- Modified 03.11
ramdatareg.vhd
--**********************************************************************************************
-- RAM data register for the AVR Core
-- Version 0.1
-- Modified 02.11.2002
-- Designed by Ruslan
avr_core.vhd
library IEEE;
use IEEE.std_logic_1164.all;
USE IEEE.std_logic_arith.all;
USE IEEE.std_logic_unsigned.all;
entity avr_core is port
(
cp2 : in std_logic;
ireset : in std_logic;
cpuwai
palbroken.vhd
-------------------------------------------------------------------------------
-- prgramdac.vhd
--
-- Author(s): Ashley Partis and Jorgen Peddersen
-- Created: Dec 2000
-- Last Modifie