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找到约 10,000 项符合
Logic Analyzer 的代码
sram_2.vhd
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_ARITH.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;
ENTITY SRAM_2 IS
PORT(P0I: IN STD_LOGIC_VECTOR(7 DOWNTO 0);
P0T: OUT STD_LOGIC_VECT
sram_rslow.vhd
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;
ENTITY SRAM_R IS
PORT(
DATASIN: IN STD_LOGIC_VECTOR(7 DOWNTO 0);
DATAMOUT: OUT STD_LOGIC_VECTOR(7 DOWNTO
sram_r.vhd
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;
ENTITY SRAM_R IS
PORT(
DATASIN: IN STD_LOGIC_VECTOR(7 DOWNTO 0);
DATAMOUT: OUT STD_LOGIC_VECTOR(7 DOWNTO
vga.vhd
library IEEE;
use IEEE.std_logic_1164.all;
package vga_pckg is
component vga
generic (
FREQ : natural := 50_000; -- master clock frequency (in KHz)
CLK_DIV
songer.vhd
LIBRARY IEEE; -- 硬件演奏电路顶层设计
USE IEEE.STD_LOGIC_1164.ALL;
ENTITY Songer IS
PORT ( CLK4 : IN STD_LOGIC; --音调频率信号
CLK6 :
songer.vhd.bak
LIBRARY IEEE; -- 硬件演奏电路顶层设计
USE IEEE.STD_LOGIC_1164.ALL;
ENTITY Songer IS
PORT ( CLK1 : IN STD_LOGIC; --音调频率信号
CLK2 :
divfsm.vhd
----------------------------------------------------
--
-- VHDL code generated by Visual HDL
--
-- Design Unit:
-- ------------
-- Unit Name : DIV_FSM_CU
-- Library Name
demux74155.vhd.bak
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
entity demux74155 is
port(din: in std_logic;
s: in std_logic_vector(1 downto 0);
y: out st
demux74155.vhd
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
entity demux74155 is
port(din: in std_logic;
s: in std_logic_vector(1 downto 0);
y: out st
division.vhd
library IEEE;
use IEEE.STD_LOGIC_1164.all;
use IEEE.STD_LOGIC_UNSIGNED.all;
use IEEE.STD_LOGIC_ARITH.all;
entity division is
generic(SIZE: INTEGER := 8);
port(reset: in STD_LOGI