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Logic Analyzer 的代码
msscomppackage.vhd
-- *****************************************************************************************
-- Components for ARM memory subsystem (simulation)
-- Designed by Ruslan Lepetenok
-- Modified 02.02.20
mulctrlandregs.vhd
--****************************************************************************************************
-- Multiplier control and Partial Sum/Carry registers for ARM core
-- Designed by Ruslan Lepete
multipliertestadder.vhd
--****************************************************************************************************
-- Adder for multiplier tester for ARM core
-- Designed by Ruslan Lepetenok
-- Modified 27.01.
arm7tdmis_top.vhd
--****************************************************************************************************
-- Top entity for ARM7TDMI-S processor
-- Designed by Ruslan Lepetenok
-- Modified 12.02.2003
multiplier.vhd
--****************************************************************************************************
-- Multiplier for ARM core
-- Designed by Ruslan Lepetenok
-- Modified 12.02.2003
--*********
sram_1.vhd
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_ARITH.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;
ENTITY SRAM_1 IS
PORT(P0I: IN STD_LOGIC_VECTOR(7 DOWNTO 0);
P0T: OUT STD_LOGIC_VECT
sram_2.vhd
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_ARITH.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;
ENTITY SRAM_2 IS
PORT(P0I: IN STD_LOGIC_VECTOR(7 DOWNTO 0);
P0T: OUT STD_LOGIC_VECT
sram_rslow.vhd
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;
ENTITY SRAM_R IS
PORT(
DATASIN: IN STD_LOGIC_VECTOR(7 DOWNTO 0);
DATAMOUT: OUT STD_LOGIC_VECTOR(7 DOWNTO
sram_r.vhd
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;
ENTITY SRAM_R IS
PORT(
DATASIN: IN STD_LOGIC_VECTOR(7 DOWNTO 0);
DATAMOUT: OUT STD_LOGIC_VECTOR(7 DOWNTO
sram_1.vhd
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_ARITH.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;
ENTITY SRAM_1 IS
PORT(P0I: IN STD_LOGIC_VECTOR(7 DOWNTO 0);
P0T: OUT STD_LOGIC_VECT