代码搜索结果

-- download from: www.pld.com.cn & www.fpga.com.cn entity testbench is end; ------------------------------------------------------------------------ -- testbench for 8-bit adder ------------

------------------------------------------------------------------------ -- Single-bit adder ------------------------------------------------------------------------ library IEEE; use IEEE.std_log

-- A Variety of Adder Styles -- download from: www.fpga.com.cn & www.pld.com.cn ------------------------------------------------------------------------ -- Single-bit adder -----------------------

library ieee; use ieee.std_logic_1164.all; package my_pkg is component div1024--1Hz_generator component Port( clk: in std_logic;--from system clock(1024Hz) f1hz : out std_logic);-- 1H

--shiftrne.vhd n-bit left-to-right shift register --with parallel load and enable library ieee ; use ieee.std_logic_1164.all ; entity shiftrne is generic ( n : integer := 7 ) ; port ( r : i

--divider.vhd n-bit divider library ieee; use ieee.std_logic_1164.all; use ieee.std_logic_unsigned.all ; use work.components.all ; entity divider is generic ( n : integer := 7 ) ; port ( c

--shiftlne.vhd n-bitright-to-left shift register --with parallel load and enable library ieee ; use ieee.std_logic_1164.all ; entity shiftlne is generic ( n : integer := 7 ) ; port( r : in s

-- File: uC_interface.vhd -- -- Author: Jennifer Jenkins -- Philips Semiconductor -- Purpose: Description of an interface with a ucontroller/uprocessor -- (i.e. Motorola 68000)

-- Generated by Viterbi Compiler 4.1.0 [Altera, IP Toolbench v1.2.5 build28] -- ************************************************************ -- THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE

library ieee; use ieee.std_logic_1164.all; use ieee.std_logic_unsigned.all; entity control is port(q:in std_logic_vector(1 downto 0); codeout:in std_logic; am,fout:in std_logic_vecto