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Logic Analyzer 的代码
cnt_reg.vhd
LIBRARY IEEE;
USE IEEE.std_logic_1164.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;
-----------------------------------------------------------------
--Entity Definition
---------------------------
cnt_reg.vhd.bak
LIBRARY IEEE;
USE IEEE.std_logic_1164.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;
-----------------------------------------------------------------
--Entity Definition
---------------------------
usb_new_usbvpb_top_str.vhdl
--------------------------------------------------------------------------------
--
-- P H I L I P S C O M P A N Y R E S T R I C T E D
--
-- Copyright
usb_new_usbpvci_ent.vhdl
--------------------------------------------------------------------------------
--
-- P H I L I P S C O M P A N Y R E S T R I C T E D
--
-- Copyright
xspcore.vhd
--------------------------------------------------------------------------------
-- Copyright (c) 2000 by Trenz Electronic.
-- Duenner Kirchweg 77, 32257 Buende, Germany, www.trenz-electronic.de
--
xspuc.vhd
--------------------------------------------------------------------------------
-- Copyright (c) 2000 by Trenz Electronic.
-- Duenner Kirchweg 77, 32257 Buende, Germany, www.trenz-electronic.de
--
xspusb.vhd
--------------------------------------------------------------------------------
-- Copyright (c) 2000 by Trenz Electronic.
-- Duenner Kirchweg 77, 32257 Buende, Germany, www.trenz-electronic.de
--
mydesign.vhd
LIBRARY IEEE;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;
USE IEEE.STD_LOGIC_1164.aLL;
ENTITY mydesign IS
PORT(D:IN STD_LOGIC_VECTOR(7 DOWNTO 0);
CLK,EOC:IN STD_LOGIC;
CLK1:IN STD_LOGIC
pilchard.vhd
library ieee;
use ieee.std_logic_1164.all;
entity pilchard is
port (
PADS_exchecker_reset: in std_logic;
PADS_dimm_ck: in std_logic;
PADS_dimm_cke: in std_logic_vector(1 downto 0);
PADS_dimm_ras:
fft.cmp
-- Generated by FFT 7.1 [Altera, IP Toolbench 1.3.0 Build 177]
-- ************************************************************
-- THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
-- ********