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Logic Analyzer 的代码
mux4w8.vhd
-- output of CoreGen module generator
-- $Header: mux4VHT.vhd,v 1.2 1998/06/15 17:58:03 tonyw Exp $
-- ************************************************************************
-- Copyright 1996-19
rsub16.vhd
-- output of CoreGen module generator
-- $Header: subreVHT.vhd,v 1.3 1998/06/15 17:53:11 tonyw Exp $
-- ************************************************************************
-- Copyright 1996-1
xspcore.vhd
--------------------------------------------------------------------------------
-- Copyright (c) 2000 by Trenz Electronic.
-- Duenner Kirchweg 77, 32257 Buende, Germany, www.trenz-electronic.de
--
xspuc.vhd
--------------------------------------------------------------------------------
-- Copyright (c) 2000 by Trenz Electronic.
-- Duenner Kirchweg 77, 32257 Buende, Germany, www.trenz-electronic.de
--
xspusb.vhd
--------------------------------------------------------------------------------
-- Copyright (c) 2000 by Trenz Electronic.
-- Duenner Kirchweg 77, 32257 Buende, Germany, www.trenz-electronic.de
--
openlock.vhd
library ieee;
use ieee.std_logic_1164.all;
entity openlock is
port( clk : in std_logic;
change : in std_logic;
test : in std_logic;
code0 : in std_logic_vector(3 downto 0);
speaker.vhd
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;
ENTITY SPEAKER IS
PORT(CLK:IN STD_LOGIC;
TONE:IN STD_LOGIC_VECTOR(10 DOWNTO 0);
SPKS:OUT STD_LOGIC);
END SPEAK
wrground.vhd
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
-- Uncomment the following lines to use the declarations that are
-- provided for ins
加法器描述.txt
-- A Variety of Adder Styles
-- download from: www.fpga.com.cn & www.pld.com.cn
------------------------------------------------------------------------
-- Single-bit adder
-----------------------
lc2.vhd
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
entity lc2 is
port(
en, ien: in std_logic;
oen: out std_logic;
reset: in std_logic
);
end lc2;
arc