speaker.vhd

出血FPGA,用VHDL做的音乐盒

LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;
ENTITY SPEAKER IS
	PORT(CLK:IN STD_LOGIC;
		 TONE:IN STD_LOGIC_VECTOR(10 DOWNTO 0);
		 SPKS:OUT STD_LOGIC);
END SPEAKER;
ARCHITECTURE MA OF SPEAKER IS
SIGNAL PRECLK,FULLSPKS:STD_LOGIC;
BEGIN
	DIVIDECLK:PROCESS(CLK)
	VARIABLE COUNT4:STD_LOGIC_VECTOR(3 DOWNTO 0);
	BEGIN
		PRECLK<='0';
		IF(COUNT4>11)THEN
			PRECLK<='1';
			COUNT4:="0000";
		ELSIF(CLK'EVENT AND CLK='1')THEN
			COUNT4:=COUNT4+1;
		END IF;
	END PROCESS;
	GENSPKS:PROCESS(PRECLK,TONE)
	VARIABLE COUNT11:STD_LOGIC_VECTOR(10 DOWNTO 0);
	BEGIN
		IF(PRECLK'EVENT AND PRECLK='1')THEN
			IF(COUNT11=16#7FF#)THEN
				COUNT11:=TONE;
				FULLSPKS<='1';
			ELSE
				COUNT11:=COUNT11+1;
				FULLSPKS<='0';
			END IF;
		END IF;
	END PROCESS;
END MA;