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Logic Analyzer 的代码
my_pkg.vhd
library ieee;
use ieee.std_logic_1164.all;
package my_pkg is
component div1024--1Hz_generator component
Port( clk: in std_logic;--from system clock(1024Hz)
f1hz : out std_logic);-- 1H
shiftrne.vhd
--shiftrne.vhd n-bit left-to-right shift register
--with parallel load and enable
library ieee ;
use ieee.std_logic_1164.all ;
entity shiftrne is
generic ( n : integer := 7 ) ;
port (
r : i
divider.vhd
--divider.vhd n-bit divider
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all ;
use work.components.all ;
entity divider is
generic ( n : integer := 7 ) ;
port (
c
shiftlne.vhd
--shiftlne.vhd n-bitright-to-left shift register
--with parallel load and enable
library ieee ;
use ieee.std_logic_1164.all ;
entity shiftlne is
generic ( n : integer := 7 ) ;
port(
r : in s
dds_vhdl.vhd
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
entity dds_vhdl is
port(clk:in std_logic;
fword:in std_logic_vector(7 downto 0);
pword:in std_logic_ve
main.vhd
--************************************************************
--
-- Project Name: Timer
-- File Name : main.vhd(top level)
-- Function : This is a basic timer,
-- use 2 key to adjust
keydetc.vhd
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity keydetc is
Port ( clk_5ms :in std_logic;
-- clk_1us :in std_logic;
ethernet.vhd
-------------------------------------------------------------------------------
-- ethernet.vhd
--
-- Author(s): Ashley Partis and Jorgen Peddersen
-- Created: Jan 2001
-- Last Modified
cpu_16.vhdl
library IEEE;
library UNISIM;
use ieee.std_logic_1164.all;
use UNISIM.VComponents.all;
entity CPU_16 is
port(
CLK: in std_logic;
RST: in std_logic;
Dbus: inout std_logic_vector(15 dow
mc8051_ramx_.vhd
-------------------------------------------------------------------------------
-- --
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