dds_vhdl.vhd

基于FPGA的直接数字频率合成器（DDS）设计 （源程序）

library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
entity dds_vhdl is
  port(clk:in std_logic;
       fword:in std_logic_vector(7 downto 0);
       pword:in std_logic_vector(7 downto 0); 
       fout: out std_logic_vector(7 downto 0);
       pout: out std_logic_vector(7 downto 0));
end;
architecture one of dds_vhdl is
   component reg16b
     port(load:in std_logic;
          din:in std_logic_vector(15 downto 0);
          dout:out std_logic_vector(15 downto 0));
  end component;
   component reg8b
     port(load:in std_logic;
          din:in std_logic_vector(7 downto 0);
          dout:out std_logic_vector(7 downto 0));
  end component;
    component adder16b
     port(a:in std_logic_vector(15 downto 0);
          b:in std_logic_vector(15 downto 0);
          s:out std_logic_vector(15 downto 0));
  end component;
   component adder8b
     port(a:in std_logic_vector(7 downto 0);
          b:in std_logic_vector(7 downto 0);
          s:out std_logic_vector(7 downto 0));
  end component;
    component sin_rom
     port(address:in std_logic_vector(7 downto 0);
          inclock:in std_logic;
          q:out std_logic_vector(7 downto 0));
  end component;
     signal f16b:std_logic_vector(15 downto 0);
     signal d16b:std_logic_vector(15 downto 0);
     signal din16b:std_logic_vector(15 downto 0);
     signal p8b:std_logic_vector(7 downto 0);
     signal lin8b:std_logic_vector(7 downto 0);
     signal sin8b:std_logic_vector(7 downto 0);
 begin
   f16b(15 downto 8)<=fword;f16b(7 downto 4)<="0000";
   f16b(3 downto 0)<="0000";p8b<=pword;
   u1:adder16b port map(a=>f16b,b=>d16b,s=>din16b);
   u2:reg16b port map(dout=>d16b,din=>din16b,load=>clk);
   u3:sin_rom port map(address=>sin8b,q=>fout,inclock=>clk);
   u4:adder8b port map(a=>p8b,b=>d16b(15 downto 8),s=>lin8b);
   u5:reg8b port map(dout=>sin8b,din=>lin8b,load=>clk);
   u6:sin_rom port map(address=>d16b(15 downto 8),q=>pout,inclock=>clk);
end;