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Logic Analyzer 的代码
reg_pc.vhd
-- "reg_pc.vhd"
--
-- Copyright (C) 1998 Ernesto Romani (romani@ascu.unian.it)
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU Genera
reg_s.vhd
-- "reg_s.vhd"
--
-- Copyright (C) 1998 Ernesto Romani (romani@ascu.unian.it)
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General
reg_8t.vhd
-- "reg_8t.vhd"
--
-- Copyright (C) 1998 Ernesto Romani (romani@ascu.unian.it)
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU Genera
dds_vhdl.vhd
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;
ENTITY DDS_VHDL IS -- 顶层设计
PORT ( CLKK : IN STD_LOGIC;
FWORD
commcore.vhd
library IEEE;
use IEEE.std_logic_1164.all;
use ieee.numeric_std.all;
entity benif_32reg_24bmem is
port (
-- Interface clock.
CLK: in STD_LOGIC;
-- Global reset.
bcdconvtb.vhd
--
-- Copyright (C) Doulos Ltd 2001
--
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
use STD.textio.all;
entity BCDConvTB is
end;
architecture Bench of BCDConvTB is
bcdconv.vhd
--
-- Copyright (C) Doulos Ltd 2001
--
library IEEE;
use IEEE.std_logic_1164.all;
entity BCDConv is
generic (N : positive); -- number of digits
port (Clock : in std_logic;
vhdl-ysw.txt
第一个CNT60实现秒钟计时功能，第二个CNT60实现分钟的计时功能，CTT3完成两小时的计时功能。秒钟计时模块的进位端和开关K1相与提供分钟的计时模块使能，当秒种计时模块计时到59时向分种计时模块进位，同时自己清零。同理分种计时模块到59时向CTT3小时计时模块进位，到1小时59分59秒时，全部清零。同时，开关K1可以在两小时内暂停秒钟计时模块，分钟计时模块和小时计时模块。各模块的VHDL语言描 ...
ball.vhd
--乒乓球灯模块
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
entity ball is
port(clk:in std_logic;--乒乓球灯前进时钟
clr:in std_logic;--乒乓球灯清零
way:in std_logic;--乒乓球灯前进方向
en
gh_mac_16bit_ld.vhd
-----------------------------------------------------------------------------
-- Filename: gh_MAC_16bit_ld.vhd
--
-- Description:
-- Multiply Accumulator
-- the total gain must be 1 or less
-