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Logic Analyzer 的代码
miaobiao.txt
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
entity keyin is
port(reset,start_stop,clk :in std_logic;
res,stst :out std_logic);
end entity;
architec
加法器描述.txt
-- A Variety of Adder Styles
-- download from: www.fpga.com.cn & www.pld.com.cn
------------------------------------------------------------------------
-- Single-bit adder
-----------------------
counter10.vhd
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity counter10 is
Port ( clk : in std_logic;
reset : in std_logic;
counter24.vhd
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity counter24 is
Port ( clk : in std_logic;
reset : in std_logic;
wblkzq.vhd
--WBLKZQ
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;
USE IEEE.STD_LOGIC_ARITH.ALL;
ENTITY WBLKZQ IS
PORT( RESET,SET_T,START,TEST,CLK,clk0: IN STD_LOGIC;
DA
comparator.vhd
------
-- VHDL module for a comparator
-- this module contains two implementations for the
-- comparsion. Not all synthesis tools will accept
-- both implementations. However, these two impleme
counter.vhd
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;
ENTITY counter IS
PORT(
CLKB:IN STD_LOGIC;--标准频率信号
TCLK:IN STD_LOGIC;--待测频率信号
CLR:IN STD_LOGIC;
change.vhd
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
entity change is
port
( period,clk:in std_logic;
n1,n2,n3:in std_logic_vector(3 downto 0);
m1,m2,m3:in std_logi
counter10.vhd
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
entity counter10 is
port(clk:in std_logic;
reset:in std_logic;
di
counter24.vhd
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
entity counter24 is
port(clk:in std_logic;
reset:in std_logic;