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Logic Analyzer 的代码
cpu_16_wave.vhw
-- C:\XILINX\BIN\MYCPU16
-- VHDL Test Bench created by
-- HDL Bencher 6.1i
-- Thu Nov 15 12:52:24 2007
--
-- Notes:
-- 1) This testbench has been automatically generated from
-- your Test Be
testmachine1.timesim_vhw
-- D:\CSHT\FINAL15.06.07\PROJECT\IMPORTANTVERSION
-- VHDL Test Bench created by
-- HDL Bencher 6.1i
-- Tue Jun 26 13:15:14 2007
--
-- Notes:
-- 1) This testbench has been automatically generate
testmachine1.vhw
-- D:\CSHT\FINAL15.06.07\PROJECT\IMPORTANTVERSION
-- VHDL Test Bench created by
-- HDL Bencher 6.1i
-- Tue Jun 26 13:15:11 2007
--
-- Notes:
-- 1) This testbench has been automatically generate
viterbi_block.vhd
-- -------------------------------------------------------------
--
-- Module: viterbi_block
-- Simulink Path: hdlcoderviterbi/viterbi_block
-- Created: 2009-03-24 16:24:10
-- Hierarchy Level: 0
--In1
viterbi_block.vhd
-- -------------------------------------------------------------
--
-- Module: viterbi_block
-- Simulink Path: hdlcoderviterbi/viterbi_block
-- Created: 2009-03-24 16:24:10
-- Hierarchy Level: 0
--In1
viterbi_block.vhd
-- -------------------------------------------------------------
--
-- Module: viterbi_block
-- Simulink Path: hdlcoderviterbi/viterbi_block
-- Created: 2009-03-24 16:24:10
-- Hierarchy Level: 0
--In1
top.vhd
clk, reset: in STD_LOGIC;
m_en, m_rw: out STD_LOGIC;
aBus: out STD_LOGIC_VECTOR(adrLength-1 downto 0);
dBus: inout STD_LOGIC_VECTOR(wordSize-1 downto 0);
pcX, iarX : out std_logic_v
top.vhd.bak
clk, reset: in STD_LOGIC;
m_en, m_rw: out STD_LOGIC;
aBus: out STD_LOGIC_VECTOR(adrLength-1 downto 0);
dBus: inout STD_LOGIC_VECTOR(wordSize-1 downto 0);
pcX, iarX : out std_logic_v
s59_tw.vhw
-- E:\VHDL\WAITPAST\DIG_CLK
-- VHDL Test Bench created by
-- HDL Bencher 6.1i
-- Wed Apr 18 11:36:41 2007
--
-- Notes:
-- 1) This testbench has been automatically generated from
-- your Test
m59.vhw
-- E:\VHDL\WAITPAST\DIG_CLK
-- VHDL Test Bench created by
-- HDL Bencher 6.1i
-- Wed Apr 18 11:26:00 2007
--
-- Notes:
-- 1) This testbench has been automatically generated from
-- your Test