代码搜索：Logic Analyzer
找到约 10,000 项符合「Logic Analyzer」的源代码
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www.eeworm.com/read/297458/8016523
vhd seven_seg_pio.vhd
--Legal Notice: (C)2006 Altera Corporation. All rights reserved. Your
--use of Altera Corporation's design tools, logic functions and other
--software and tools, and its AMPP partner logic functions,
www.eeworm.com/read/140651/13069703
vhd cpu.vhd
--Copyright (C) 1991-2004 Altera Corporation
--Any megafunction design, and related net list (encrypted or decrypted),
--support information, device programming or simulation file, and any other
--
www.eeworm.com/read/140650/13069720
vhd cpu.vhd
--Copyright (C) 1991-2004 Altera Corporation
--Any megafunction design, and related net list (encrypted or decrypted),
--support information, device programming or simulation file, and any other
--
www.eeworm.com/read/140648/13069846
vhd cpu.vhd
--Copyright (C) 1991-2004 Altera Corporation
--Any megafunction design, and related net list (encrypted or decrypted),
--support information, device programming or simulation file, and any other
--
www.eeworm.com/read/140647/13069876
vhd cpu.vhd
--Copyright (C) 1991-2004 Altera Corporation
--Any megafunction design, and related net list (encrypted or decrypted),
--support information, device programming or simulation file, and any other
--
www.eeworm.com/read/139799/13130864
vhd example14-2.vhd
LIBRARY IEEE;
USE IEEE.std_logic_1164.all;
PACKAGE ram_pack IS
SUBTYPE RAM_WORD IS std_logic_vector(7 downto 0);
SUBTYPE RAM_RANGE IS integer range 0 to 31;
TYPE RAM_TYPE IS array (RAM_RANGE
www.eeworm.com/read/319236/13457370
vhd gh_uart_16550_wb_wrapper.vhd
-----------------------------------------------------------------------------
-- Filename: gh_uart_16550_wb_wrapper.vhd
--
-- Description:
-- This is (ment to be) a wishbone interface
-- wrapp
www.eeworm.com/read/314805/13558614
vhw visit_memory_wave.vhw
-- C:\XILINX\BIN\MYCPU16
-- VHDL Test Bench created by
-- HDL Bencher 6.1i
-- Thu Nov 15 13:55:43 2007
--
-- Notes:
-- 1) This testbench has been automatically generated from
-- your Test Be
www.eeworm.com/read/314805/13558737
vhw alu-wave.vhw
-- E:\资料\计算机设计与实践\MYCPU16
-- VHDL Test Bench created by
-- HDL Bencher 6.1i
-- Sun Nov 11 22:53:07 2007
--
-- Notes:
-- 1) This testbench has been automatically generated from
-- your Test B
www.eeworm.com/read/314805/13558836
vhw memory_wave.vhw
-- C:\XILINX\BIN\MYCPU16
-- VHDL Test Bench created by
-- HDL Bencher 6.1i
-- Thu Nov 15 13:55:08 2007
--
-- Notes:
-- 1) This testbench has been automatically generated from
-- your Test Be