代码搜索：Logic Analyzer
找到约 10,000 项符合「Logic Analyzer」的源代码
代码结果 10,000
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vhd uart.vhd
----------------------------------------------------------------------------
-- This file is a part of the LEON VHDL model
-- Copyright (C) 1999 European Space Agency (ESA)
--
-- This library is f
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vhd tiaojia.vhd
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
entity tiaojia is
--实现调价功能
port
( flag1 : in std_logic; --调价状态标志
sure : in std
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vhd count60.vhd
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
entity count60 is
--clk 计数脉冲
--count 计数输出
--co 进位信号
port
(
clk : in std_logic;
flag2 : in std_logic;
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vhd cnt10.vhd
-- MAX+plus II VHDL Template
-- Clearable flipflop with enable
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_unsigned.all;
ENTITY cnt10 IS
PORT
(
clk,rst,en : IN STD
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vhd mc8051_ram_.vhd
-------------------------------------------------------------------------------
-- --
-- X X XXXXXX XXXXXX
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vhd alumux_.vhd
-------------------------------------------------------------------------------
-- --
-- X X XXXXXX XXXXXX
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vhd mc8051_alu_.vhd
-------------------------------------------------------------------------------
-- --
-- X X XXXXXX XXXXXX
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vhd mc8051_siu_.vhd
-------------------------------------------------------------------------------
-- --
-- X X XXXXXX XXXXXX
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vhd txmit.vhd
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
entity txmit is
port(
tx:out std_logic;
--data:in std_logic_vector(7 downto 0);
mclk_16,write:in std_logic
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vhd rxcver.vhd
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
--use ieee.std_logic_signed.all;
entity RXCVER is
--generic:constant:std_logic;
port