cnt10.vhd

用VHDL实现频率计

-- MAX+plus II VHDL Template
-- Clearable flipflop with enable

LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_unsigned.all;

ENTITY cnt10 IS

	PORT
	(
		clk,rst,en		: IN	STD_LOGIC;
		CQ				: OUT	STD_LOGIC_VECTOR(3 DOWNTO 0);
		COUT			: OUT 	STD_LOGIC
	);
	
END CNT10;

ARCHITECTURE a OF CNT10 IS
BEGIN
PROCESS (clk,RST,EN)
VARIABLE CQI: STD_LOGIC_VECTOR(3 DOWNTO 0);
	BEGIN
	IF RST = '1' THEN	CQI:=(OTHERS=>'0');
	ELSIF (clk'EVENT AND clk = '1') THEN
		IF EN = '1' THEN
			IF CQI<9 THEN CQI:=CQI+1;			
			ELSE	CQI:=(OTHERS=>'0');		
			END IF;
			END IF;
            END IF;
		IF CQI=9 THEN COUT<='1';
			ELSE COUT<='0';
		END IF;
         CQ<=CQI;
	END PROCESS;
	END a;