代码搜索：Logic Analyzer
找到约 10,000 项符合「Logic Analyzer」的源代码
代码结果 10,000
www.eeworm.com/read/415874/11049615
vhd uart_tal.vhd
--
-- uart_tal.vhd
--
-- 8-N-1 serial interface
-- conf_reg: baud_rate and 2400, HW hs on/off, DTR
-- default: 111 => baud_rate, HW hs, DTR on
--
-- Author: Martin Schoeberl martin@good-ear.co
www.eeworm.com/read/415874/11049619
vhd uart_simple_broken.vhd
--
-- uart_simple.vhd
--
-- 8-N-1 serial interface
--
-- wr, rd should be one cycle long => trde, rdrf goes 0 one cycle later
--
-- Author: Martin Schoeberl martin@good-ear.com
--
--
-- res
www.eeworm.com/read/270072/11049621
vhd cnt3.vhd
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
entity cnt3 is
port(clk,en :in std_logic;
q :buffer std_logic_vector(1 downto 0));
end cnt3;
architectur
www.eeworm.com/read/415793/11053837
vhd divider.vhd
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_unsigned.all ;
USE work.components.all ;
ENTITY divider IS
GENERIC ( N : INTEGER := 8 ) ;
PORT( Clock, Resetn : IN STD_LOGIC ;
www.eeworm.com/read/415793/11053866
vhd divider.vhd
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_unsigned.all ;
USE work.components.all ;
ENTITY divider IS
GENERIC ( N : INTEGER := 8 ) ;
PORT ( Clock : IN STD_LOGIC ;
R
www.eeworm.com/read/415793/11053884
vhd multiply.vhd
LIBRARY ieee ;
USE ieee.std_logic_1164.all ;
USE ieee.std_logic_unsigned.all ;
USE work.components.all ;
ENTITY multiply IS
GENERIC ( N : INTEGER := 8; NN : INTEGER := 16 ) ;
PORT ( Clock
www.eeworm.com/read/415793/11053931
vhd func5.vhd
LIBRARY ieee ;
USE ieee.std_logic_1164.all ;
ENTITY func5 IS
PORT ( x1, x2, x3, x4, x5, x6, x7 : IN STD_LOGIC ;
f : OUT STD_LOGIC ) ;
END func5 ;
ARCHITECTURE LogicFunc O
www.eeworm.com/read/415793/11053934
vhd example2.vhd
LIBRARY ieee;
USE ieee.std_logic_1164.all;
ENTITY example2 IS
PORT ( x1, x2, x3, x4, x5, x6, x7 : IN STD_LOGIC ;
f : OUT STD_LOGIC ) ;
END example2 ;
ARCHITECTURE LogicFunc OF ex
www.eeworm.com/read/415351/11075495
txt 米勒型状态机.txt
-- Mealy State Machine with Registered Outputs
-- dowload from: www.fpga.com.cn & www.pld.com.cn
library ieee;
use ieee.std_logic_1164.all;
entity mealy1 is port(
clk, rst: in
www.eeworm.com/read/415351/11075517
txt 带莫尔_米勒输出的状态机.txt
-- State Machine with Moore and Mealy outputs
-- dowload from: www.fpga.com.cn & www.pld.com.cn
library ieee;
use ieee.std_logic_1164.all;
entity mealy1 is port(
clk, rst: in