代码搜索:Logic Analyzer

找到约 10,000 项符合「Logic Analyzer」的源代码

代码结果 10,000
www.eeworm.com/read/394878/8204531

vhd dis.vhd

library IEEE; use IEEE.std_logic_1164.all; use IEEE.std_logic_unsigned.all; --库包含 entity DIS is port(din : in std_logic_vector(3 downto 0); -- 显示口令数据 cr_cnt :in std_logic_vector(1
www.eeworm.com/read/394872/8204692

vhd service_module.vhd

--********************************************************************************************** -- Some additional control registers for the AVR Core -- Version 0.7 20.05.2003 -- Designed by Rusla
www.eeworm.com/read/394872/8204702

vhd io_reg_file.vhd

--************************************************************************************************ -- Internal I/O registers (implemented inside the core) decoder/multiplexer -- for AVR core -- Versi
www.eeworm.com/read/394698/8211422

vhd speakera.vhd

library ieee; use ieee.std_logic_1164.all; use ieee.std_logic_unsigned.all; entity speakera is port(clk:in std_logic; tone:in std_logic_vector(10 downto 0); sp
www.eeworm.com/read/394237/8241465

vhd cntm60.vhd

--库文件,包说明 LIBRARY IEEE; USE IEEE.STD_LOGIC_1164.ALL; USE IEEE.STD_LOGIC_UNSIGNED.ALL; --实体说明一个模为60的同步计数器 ENTITY CNTM60 IS PORT(NRST:IN STD_LOGIC;--异步复位端口 LD:IN STD_LOGIC;--置数端口 CI:IN
www.eeworm.com/read/394236/8241491

vhd cnt24.vhd

--同步清零的24进制计数器 --库文件和程序包说明 LIBRARY IEEE; USE IEEE.STD_LOGIC_1164.ALL; USE IEEE.STD_LOGIC_UNSIGNED.ALL; --实体说明 ENTITY CNT24 IS PORT(CLR,CLK,CLOCK:IN STD_LOGIC; QOUT7,QOUT6,QOUT5,QOUT4,QOUT3
www.eeworm.com/read/394233/8241699

vhd cnt10.vhd

--库文件和程序包定义 --编译之前首先要set project to current file,指向当前编译文件,否则指向上一次编译文件 LIBRARY IEEE; USE IEEE.STD_LOGIC_1164.ALL; USE IEEE.STD_LOGIC_UNSIGNED.ALL;--定义了integer型及std_logic_vector 和std_logic混合运算的运算符
www.eeworm.com/read/394007/8251407

vhd lcd.vhd

library IEEE; use IEEE.STD_LOGIC_1164.ALL; use IEEE.STD_LOGIC_ARITH.ALL; use IEEE.STD_LOGIC_UNSIGNED.ALL; entity lcd is Port (A : in STD_LOGIC_VECTOR(0 to 3); B : in STD_LOG
www.eeworm.com/read/393840/8260426

vhd ddr_data_path.vhd

-- -- LOGIC CORE: DDR Data Path Module -- MODULE NAME: ddr_data_path() -- COMPANY: Northwest Logic, Inc. -- www.nwlogic.com -- -- R
www.eeworm.com/read/393840/8260444

vhd ddr_sdram_tb.vhd

--/****************************************************************************** --* --* LOGIC CORE: SDR SDRAM Controller test bench --* MODULE NAME: sdr_sdram_tb() --*