cnt24.vhd

这是二十四进制计数器的源程序

--同步清零的24进制计数器
--库文件和程序包说明
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;
--实体说明
ENTITY CNT24 IS
	PORT(CLR,CLK,CLOCK:IN STD_LOGIC;
			QOUT7,QOUT6,QOUT5,QOUT4,QOUT3,QOUT2,QOUT1,QOUT0:BUFFER STD_LOGIC);
END ENTITY CNT24;
--程序包说明
ARCHITECTURE BEHAV OF CNT24 IS
	--信号申明
	SIGNAL QH:STD_LOGIC_VECTOR(7 DOWNTO 4);
	SIGNAL QL:STD_LOGIC_VECTOR(3 DOWNTO 0);
	BEGIN
		PROCESS(CLK)IS
			BEGIN
				IF(RISING_EDGE(CLK))THEN
					IF(CLR='1')THEN
						QH<="0000";--赋值
						QL<="0000";
					ELSE
						IF(QL="1001"OR (QH="0010"AND QL="0011"))THEN
							QL<="0000";
							IF(QH="0010")THEN
								QH<="0000";
							ELSE
								QH<=QH+1;
							END IF;
						ELSE
							QL<=QL+1;
						END IF;
					END IF;
				END IF;
		END PROCESS;
	QOUT7<=QH(7);
	QOUT6<=QH(6);
	QOUT5<=QH(5);
	QOUT4<=QH(4);
	QOUT3<=QL(3);
	QOUT2<=QL(2);
	QOUT1<=QL(1);
	QOUT0<=QL(0);

--消除毛刺
		--PROCESS(CLOCK,Q)IS
			--BEGIN
				--IF(CLOCK'EVENT AND CLOCK='1')THEN
					--QOUT3<=Q(3);
					--QOUT2<=Q(2);
					--QOUT1<=Q(1);
					--QOUT0<=Q(0);
				--END IF;
		--END PROCESS;
	END ARCHITECTURE BEHAV;