代码搜索：Logic Analyzer

找到约 10,000 项符合「Logic Analyzer」的源代码

代码结果 10,000
热门代码： main.c GPIO I2C SPI UART timer interrupt ADC PWM LED
www.eeworm.com/read/215048/15076303

vhd modelctrl.vhd

library ieee; use ieee.std_logic_1164.all; use ieee.std_logic_unsigned.all; entity modelctrl is port( model: in std_logic; stanum: out std_logic_vector(6 downto 0); ctrl: out std_logi
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www.eeworm.com/read/214183/15111448

vhd conve.vhd

library IEEE; use IEEE.STD_LOGIC_1164.ALL; use IEEE.STD_LOGIC_ARITH.ALL; use IEEE.STD_LOGIC_UNSIGNED.ALL; entity convert is Port ( enable : in std_logic; clk : in std_lo
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www.eeworm.com/read/213714/15127520

txt taxijifeiqi.txt

--实验十四 出租车计费器 --里程计算模块 -- LCJS.VHD library IEEE; use IEEE.std_logic_1164.all; use ieee.std_logic_unsigned.all; use ieee.std_logic_arith.all; entity LCJS is GENERIC(--0:INTEGER:=160 ; --
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www.eeworm.com/read/213596/15129700

vhd cornaa.vhd

library ieee; use ieee.std_logic_1164.all; entity cornaa is -----LOAD 为设置密码的开关 port(clk,k1,k0,clr,load:in std_logic; -----K1，K0 分别是代表1和0的按键开关 lt:inout std_logi
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www.eeworm.com/read/213523/15130876

vhd t2t.vhd

-- MAX+plus II VHDL Template -- Clearable flipflop with enable LIBRARY ieee; USE ieee.std_logic_1164.all; ENTITY T2T IS PORT ( data : in std_logic_vector(7 downto 0); dataout, q
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www.eeworm.com/read/213523/15130879

vhd r2r.vhd

-- MAX+plus II VHDL Template -- Clearable flipflop with enable LIBRARY ieee; USE ieee.std_logic_1164.all; ENTITY R2R IS PORT ( data : in std_logic_vector(7 downto 0); dataout, q
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www.eeworm.com/read/211745/15174418

vhd txmit.vhd

library ieee; use ieee.std_logic_1164.all; use ieee.std_logic_unsigned.all; entity txmit is port( tx:out std_logic; --data:in std_logic_vector(7 downto 0); mclk_16,write:in std_logic
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www.eeworm.com/read/211745/15174419

vhd rxcver.vhd

library ieee; use ieee.std_logic_1164.all; use ieee.std_logic_arith.all; use ieee.std_logic_unsigned.all; --use ieee.std_logic_signed.all; entity RXCVER is --generic:constant:std_logic; port
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www.eeworm.com/read/211745/15174441

vhd mul3.vhd

library ieee; use ieee.std_logic_1164.all; entity mul3 is port(in1,in2,in3:std_logic_vector(7 downto 0); sela,selb,selc:in std_logic; dout:out std_logic_vector(7 downto 0) ); e
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www.eeworm.com/read/211745/15174509

vhd counter60.vhd

--counter60 library IEEE; use IEEE.std_logic_1164.all; use IEEE.std_logic_arith.all; use IEEE.std_logic_unsigned.all; entity counter60 is port(clk,clr:in std_logic; c:out std_logic;
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