代码搜索：Logic Analyzer
找到约 10,000 项符合「Logic Analyzer」的源代码
代码结果 10,000
www.eeworm.com/read/228098/14400810
vhd controllogic.vhd
--****************************************************************************************************
-- Control logic for ARM7TDMI-S processor
-- Designed by Ruslan Lepetenok
-- Modified 11.02.20
www.eeworm.com/read/228098/14400818
vhd bbusmultiplexer.vhd
--****************************************************************************************************
-- B bus multiplexer for ARM7TDMI-S processor
-- Designed by Ruslan Lepetenok
-- Modified 04.1
www.eeworm.com/read/228098/14400837
vhd datamux.vhd
--****************************************************************************************************
-- Data multiplexer for ARM memory sybsistem
-- Designed by Ruslan Lepetenok
-- Modified 07.12
www.eeworm.com/read/126738/14405536
vhd hdb3.vhd
------hdb3.vhd HDB3 coder in VHDL------
--Desinger: Long Yachun
--Date: 2004-12-10
library ieee;
use ieee.std_logic_1164.all;
entity hdb3 is
port(codein: in std_logic;
clk : i
www.eeworm.com/read/126575/14416397
vhd and4.vhd
library IEEE;
use IEEE.std_logic_1164.all;
entity and4 is
port (
a: in STD_LOGIC;
b: in STD_LOGIC;
c: in STD_LOGIC;
d: in STD_LOGIC;
y: out STD_LO
www.eeworm.com/read/126575/14416408
keyscan66
-- KEY BOARD
-------------------------------------
--000 *A* *B* *C* *D* *E* *F*
--001 *G* *H* *I* *J* *K* *L*
--010 *M* *N* *O* *P* *Q* *R*
--011 *S
www.eeworm.com/read/227189/14437607
txt 米勒型状态机.txt
-- Mealy State Machine with Registered Outputs
-- dowload from: www.fpga.com.cn & www.pld.com.cn
library ieee;
use ieee.std_logic_1164.all;
entity mealy1 is port(
clk, rst: in
www.eeworm.com/read/227189/14437624
txt 带莫尔_米勒输出的状态机.txt
-- State Machine with Moore and Mealy outputs
-- dowload from: www.fpga.com.cn & www.pld.com.cn
library ieee;
use ieee.std_logic_1164.all;
entity mealy1 is port(
clk, rst: in
www.eeworm.com/read/227189/14437633
txt 莫尔型状态机2.txt
-- Moore State Machine with Concurrent Output Logic
-- dowload from: www.fpga.com.cn & www.pld.com.cn
library ieee;
use ieee.std_logic_1164.all;
entity moore1 is port(
clk, rst:
www.eeworm.com/read/227189/14437650
txt 莫尔型状态机1.txt
-- Moore State Machine with explicit state encoding
-- dowload from: www.fpga.com.cn & www.pld.com.cn
library ieee;
use ieee.std_logic_1164.all;
entity moore2 is port(
clk, rst: