and4.vhd

本人初学VHDL时编的比较系统的VHDL源程序 巨实用

library IEEE;
use IEEE.std_logic_1164.all;

entity and4 is
    port (
        a: in STD_LOGIC;
        b: in STD_LOGIC;
        c: in STD_LOGIC;
        d: in STD_LOGIC;
        y: out STD_LOGIC
    );
end and4;

architecture and4_arch of and4 is
begin
  y<=a  and  b  and  c  and d ;-- <<enter your statements here>>
end and4_arch;