代码搜索：Logic Analyzer
找到约 10,000 项符合「Logic Analyzer」的源代码
代码结果 10,000
www.eeworm.com/read/252132/12300651
vhd multiply.vhd
LIBRARY ieee ;
USE ieee.std_logic_1164.all ;
USE ieee.std_logic_unsigned.all ;
USE work.components.all ;
ENTITY multiply IS
GENERIC ( N : INTEGER := 8; NN : INTEGER := 16 ) ;
PORT ( Clock
www.eeworm.com/read/252132/12300715
vhd func5.vhd
LIBRARY ieee ;
USE ieee.std_logic_1164.all ;
ENTITY func5 IS
PORT ( x1, x2, x3, x4, x5, x6, x7 : IN STD_LOGIC ;
f : OUT STD_LOGIC ) ;
END func5 ;
ARCHITECTURE LogicFunc O
www.eeworm.com/read/252132/12300720
vhd example2.vhd
LIBRARY ieee;
USE ieee.std_logic_1164.all;
ENTITY example2 IS
PORT ( x1, x2, x3, x4, x5, x6, x7 : IN STD_LOGIC ;
f : OUT STD_LOGIC ) ;
END example2 ;
ARCHITECTURE LogicFunc OF ex
www.eeworm.com/read/150153/12308910
vhd cnt24.vhd
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
entity cnt24 is
port(clk: in std_logic;
clr: in std_logic;
ena: in std_logic;
cq1: out std_logic_vector(3 downto 0
www.eeworm.com/read/338077/12325566
vhd kongzhi.vhd
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
entity kongzhi is
port(
clk:in std_logic;
reset:std_logic;
a:out std_logic_vector(2 downto 0);
b:o
www.eeworm.com/read/149929/12330497
vhd cntm100v.vhd
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.std_logic_unsigned.ALL;
--------------------
ENTITY cntm100v IS
PORT(en: IN std_logic;
clr:in std_logic;
clk:in
www.eeworm.com/read/149929/12330533
vhd cntm24v.vhd
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.std_logic_unsigned.ALL;
--------------------
ENTITY cntm24v IS
PORT(en: IN std_logic;
clr:in std_logic;
clk:in s
www.eeworm.com/read/149929/12330913
vhd cntm60v.vhd
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.std_logic_unsigned.ALL;
--------------------
ENTITY cntm60v IS
PORT(en: IN std_logic;
clr:in std_logic;
clk:in
www.eeworm.com/read/149929/12331050
vhd cntm100v.vhd
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.std_logic_unsigned.ALL;
--------------------
ENTITY cntm100v IS
PORT(en: IN std_logic;
clr:in std_logic;
clk:in
www.eeworm.com/read/149929/12331414
vhd cntm24v.vhd
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.std_logic_unsigned.ALL;
--------------------
ENTITY cntm24v IS
PORT(en: IN std_logic;
clr:in std_logic;
clk:in s