cnt24.vhd

福州大学EDA选修课所有实验课程代码。VHDL语言描述（vhd）

library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
entity cnt24 is
port(clk:	in std_logic;
	clr:	in std_logic;
	ena:	in std_logic;
	cq1:	out std_logic_vector(3 downto 0);
		cq2:	out std_logic_vector(3 downto 0);
	carry_out:	out std_logic);
end cnt24;

architecture behv of cnt24 is
	signal low: std_logic_vector(3 downto 0);
	signal high: std_logic_vector(3 downto 0);
begin
	process(clk,clr,ena)
	begin
		if clr='1' then
			low<=(others=>'0');
			high<=(others=>'0');
		elsif clk'event and clk='1' then
			if ena='1' then
			
				if high<2 then
					if low<9 then
						low<= low+1;			--low for 10
			       else
				        low<=(others=>'0');
			       end if;
			    else
			       if low<3 then
						low<= low+1;			--low for 4
			       else
				        low<=(others=>'0');
			       end if;
			    end if;
			    
			    if low=0 then
			    	if high<2 then
			    		high<=high+1;			--high for 3
			    	else
			    		high<=(others=>'0');
			    	end if;
				end if;

			end if;
		end if;
	end process;
	process(low)
	begin
		if low=0 then
			carry_out<='1';
		else
			carry_out<='0';
		end if;
	end process;
	cq1<=low;
	cq2<=high;
end behv;