代码搜索：Logic Analyzer
找到约 10,000 项符合「Logic Analyzer」的源代码
代码结果 10,000
www.eeworm.com/read/339666/12211079
vhd rxcver.vhd
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
--use ieee.std_logic_signed.all;
entity RXCVER is
--generic:constant:std_logic;
port
www.eeworm.com/read/151402/12216009
txt 32fenpinqi.txt
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;
ENTITY kkk IS
PORT(CLK,EN: IN STD_LOGIC;
OUTPUT: OUT STD_LOGIC);
END kkk;
ARCHITECTURE behav OF kkk IS
www.eeworm.com/read/151107/12234939
vhd erg2810_vhd.vhd
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
ENTITY erg2810_vhd IS
PORT(
a,b,c : IN STD_LOGIC;
y : OUT STD_LOGIC);
END erg2810_vhd;
ARCHITECTURE vhdl OF erg2810_vhd IS
BEGIN
y
www.eeworm.com/read/339074/12261005
vhd parallel.vhd
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;
USE IEEE.STD_LOGIC_ARITH.ALL;
ENTITY PARALLEL IS
PORT(MCU_IN:IN STD_LOGIC_VECTOR(7 DOWNTO 0);
EN,TXD:IN STD_LOGIC;
www.eeworm.com/read/339074/12261075
vhd mcu_fpga.vhd
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;
USE IEEE.STD_LOGIC_ARITH.ALL;
ENTITY MCU_FPGA IS
PORT(MCU_IN:IN STD_LOGIC_VECTOR(7 DOWNTO 0);
EN,TXD:IN STD_LOGIC;
www.eeworm.com/read/339074/12262243
vhd sanjiao.vhd
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
entity sanjiao is
port( en,clk:in std_logic;
co:out std_logic_vector(9 downto 0));
end sanjiao
www.eeworm.com/read/338889/12274859
txt fpga程序.txt
作为FPGA的爱好者，我们希望能够更好的交流，更多的了解使用FPGA我们还能作哪些事情，能做到什么程度，能做到什么效果，这样大家多这个行业会有更多的了解。
大家可以把一些不涉及秘密的源代码公开于大家讨论。这样不仅能为初学者提供学习的最佳资料（看一些枯燥的书是没多大用的，个人感觉），也可以让自己的项目能够得到更多人的欣赏！
为了抛砖引玉，我先送上几个源代码
多进制数字频率调制(MFSK ...
www.eeworm.com/read/252473/12280580
vhd fenpin.vhd
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity taxi is
port ( clk_240 :in std_logic;
www.eeworm.com/read/252132/12300590
vhd divider.vhd
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_unsigned.all ;
USE work.components.all ;
ENTITY divider IS
GENERIC ( N : INTEGER := 8 ) ;
PORT( Clock, Resetn : IN STD_LOGIC ;
www.eeworm.com/read/252132/12300624
vhd divider.vhd
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_unsigned.all ;
USE work.components.all ;
ENTITY divider IS
GENERIC ( N : INTEGER := 8 ) ;
PORT ( Clock : IN STD_LOGIC ;
R